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From: Sergey Fedorov <serge.fdrv@gmail.com>
Message-ID: <56AB97C8.7050809@gmail.com>
Date: Fri, 29 Jan 2016 19:48:08 +0300
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Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 8/8] target-arm: ignore
 ELR_ELx[1] for exception return to 32-bit ARM mode
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>, qemu-arm@nongnu.org, patches@linaro.org

On 14.01.2016 21:34, Peter Maydell wrote:
> The architecture requires that for an exception return to AArch32 the
> low bits of ELR_ELx are ignored when the PC is set from them:
>  * if returning to Thumb mode, ignore ELR_ELx[0]
>  * if returning to ARM mode, ignore ELR_ELx[1:0]
>
> We were only squashing bit 0; also squash bit 1 if the SPSR T bit
> indicates this is a return to ARM code.

Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/op_helper.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 5789ccb..171d6b8 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -738,7 +738,11 @@ void HELPER(exception_return)(CPUARMState *env)
>          }
>          aarch64_sync_64_to_32(env);
>  
> -        env->regs[15] = env->elr_el[cur_el] & ~0x1;
> +        if (spsr & CPSR_T) {
> +            env->regs[15] = env->elr_el[cur_el] & ~0x1;
> +        } else {
> +            env->regs[15] = env->elr_el[cur_el] & ~0x3;
> +        }
>      } else {
>          env->aarch64 = 1;
>          pstate_write(env, spsr);