From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aPCXd-0007WK-Kb for qemu-devel@nongnu.org; Fri, 29 Jan 2016 12:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aPCXb-0007Fs-Nu for qemu-devel@nongnu.org; Fri, 29 Jan 2016 12:09:00 -0500 References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-2-git-send-email-peter.maydell@linaro.org> <56AB972A.5010007@gmail.com> From: Sergey Fedorov Message-ID: <56AB9CA3.4050007@gmail.com> Date: Fri, 29 Jan 2016 20:08:51 +0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Patch Tracking , QEMU Developers , qemu-arm , "Edgar E. Iglesias" , Paolo Bonzini , =?UTF-8?Q?Alex_Benn=c3=a9e?= On 29.01.2016 20:05, Peter Maydell wrote: > On 29 January 2016 at 16:45, Sergey Fedorov wrote: >> > On 14.01.2016 21:34, Peter Maydell wrote: >>> >> Support EL2 and EL3 in arm_el_is_aa64() by implementing the >>> >> logic for checking the SCR_EL3 and HCR_EL2 register-width bits >>> >> as appropriate to determine the register width of lower exception >>> >> levels. >> > >> > Reviewed-by: Sergey Fedorov > Thanks for the review, but this series went into master last week :-) Heh, I missed that somehow :) Anyway, great patches!