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From: Christopher Covington <cov@codeaurora.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: Aaron Lindsay <alindsay@codeaurora.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [RFC 09/14] Implement remaining PMU functionality
Date: Tue, 2 Feb 2016 18:01:23 -0500	[thread overview]
Message-ID: <56B13543.7000801@codeaurora.org> (raw)
In-Reply-To: <CAKmqyKMKSaUbDbGDdTndkPoYFM+0BhYWrmqKr9EZaO-JneOQQA@mail.gmail.com>

Hi Alistair,

On 02/02/2016 04:22 PM, Alistair Francis wrote:
> On Wed, Aug 5, 2015 at 9:51 AM, Christopher Covington
> <cov@codeaurora.org> wrote:
>> This adds logic to increment PMEVCNTR's based on different event inputs,
>> implements all remaining CP registers, and triggers an interrupt on
>> event overflow.
> 
> We (Xilinx) need parts of this patch to avoid kernel panics when
> booting the 4.4 Linux kernel. Have you done any more work on it? If
> you can send out a pach set I'm happy to have a look at it.

This issue sounds related to Lorenzo Piersali's patch arm64: kernel: fix
PMUv3 registers unconditional access.

As for the status of our TCG PMU patches, unfortunately, last I recall,
I was writing some kvm-unit-tests that Drew wanted me to test against
the KVM PMU, which required real hardware. I got distracted with using
an upstream kernel and a certain distribution on the hardware and have
yet to return.

Cov

-- 
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2016-02-02 23:01 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-05 16:51 [Qemu-devel] RFC: ARM Semihosting, PMU, and BBV Changes Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 01/14] Make unknown semihosting calls non-fatal Christopher Covington
2015-08-06  9:11   ` Alex Bennée
2015-08-06 17:59     ` Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 02/14] Added semihosting support for A64 in full-system mode Christopher Covington
2015-08-11 18:16   ` Peter Maydell
2015-08-05 16:51 ` [Qemu-devel] [RFC 03/14] Fix makefile Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 04/14] Modify load exclusive/store exclusive to use physical addresses with the monitor Christopher Covington
2015-09-23 17:19   ` [Qemu-devel] [PATCHv2] target-arm: Use physical addresses for ldrex/strex Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 05/14] Fixed TLB invalidate ops Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 06/14] Added support for block profiling for AArch32 and Aarch64 Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 07/14] Add PMU to ARM virt platform Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 08/14] Add instruction-counting infrastructure to target-arm Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 09/14] Implement remaining PMU functionality Christopher Covington
2016-02-02 21:22   ` Alistair Francis
2016-02-02 23:01     ` Christopher Covington [this message]
2016-02-02 23:22       ` Alistair Francis
2016-02-03 18:37         ` Peter Maydell
2016-02-04  0:37           ` Alistair Francis
2015-08-05 16:51 ` [Qemu-devel] [RFC 10/14] bbvec: Move mode/PID change detection to register writes Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 11/14] Print bbvec stats on 'magic' exceptions Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 12/14] bbvec: Detect mode changes after uncached_cpsr update Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 13/14] Enable negative icount values for QEMU Christopher Covington
2015-08-05 16:51 ` [Qemu-devel] [RFC 14/14] bbvec: Properly detect conditional thumb2 branching instructions Christopher Covington
2015-08-11 15:27 ` [Qemu-devel] RFC: ARM Semihosting, PMU, and BBV Changes Peter Maydell

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