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([2a01:e0a:466:71c0:703f:24ee:3c57:e184]) by smtp.gmail.com with ESMTPSA id v7sm5815129wrp.45.2020.06.17.01.17.56 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jun 2020 01:17:58 -0700 (PDT) From: Christophe de Dinechin Message-Id: <56BCFEC0-DEEF-46A9-9BC4-8A75ABD158CF@redhat.com> Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: ovmf / PCI passthrough impaired due to very limiting PCI64 aperture Date: Wed, 17 Jun 2020 10:17:55 +0200 In-Reply-To: <20200616171021.GV2366737@habkost.net> To: Eduardo Habkost References: <99779e9c-f05f-501b-b4be-ff719f140a88@canonical.com> <20200616165043.24y2cp53axk7uggy@sirius.home.kraxel.org> <20200616165746.GH2788@work-vm> <20200616171021.GV2366737@habkost.net> X-Mailer: Apple Mail (2.3608.80.23.2.2) X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: multipart/alternative; boundary="Apple-Mail=_12CD78C0-16CE-40CF-8F46-CE5829A775C8" Received-SPF: pass client-ip=207.211.31.81; envelope-from=cdupontd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/17 01:42:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pedro.principeza@canonical.com, dann.frazier@canonical.com, "Guilherme G. Piccoli" , "Dr. David Alan Gilbert" , christian.ehrhardt@canonical.com, qemu-devel@nongnu.org, Gerd Hoffmann , lersek@redhat.com, fw@gpiccoli.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --Apple-Mail=_12CD78C0-16CE-40CF-8F46-CE5829A775C8 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > Le 16 Jun 2020 =C3=A0 19:10, Eduardo Habkost a =C3= =A9crit : >=20 > On Tue, Jun 16, 2020 at 05:57:46PM +0100, Dr. David Alan Gilbert wrote: >> * Gerd Hoffmann (kraxel@redhat.com) wrote: >>> Hi, >>>=20 >>>> (a) We could rely in the guest physbits to calculate the PCI64 apertur= e. >>>=20 >>> I'd love to do that. Move the 64-bit I/O window as high as possible an= d >>> use -- say -- 25% of the physical address space for it. >>>=20 >>> Problem is we can't. >>>=20 >>>> failure. Also, if the users are not setting the physbits in the guest, >>>> there must be a default (seems to be 40bit according to my experiments= ), >>>> seems to be a good idea to rely on that. >>>=20 >>> Yes, 40 is the default, and it is used *even if the host supports less >>> than that*. Typical values I've seen for intel hardware are 36 and 39. >>> 39 is used even by recent hardware (not the xeons, but check out a >>> laptop or a nuc). >>>=20 >>>> If guest physbits is 40, why to have OVMF limiting it to 36, right? >>>=20 >>> Things will explode in case OVMF uses more physbits than the host >>> supports (host physbits limit applies to ept too). In other words: OVM= F >>> can't trust the guest physbits, so it is conservative to be on the safe >>> side. >>>=20 >>> If we can somehow make a *trustable* physbits value available to the >>> guest, then yes, we can go that route. But the guest physbits we have >>> today unfortunately don't cut it. >>=20 >> In downstream RH qemu, we run with host-physbits as default; so it's rea= sonably >> trustworthy; of course that doesn't help you across a migration between >> hosts with different sizes (e.g. an E5 Xeon to an E3). >> Changing upstream to do the same would seem sensible to me, but it's not >> a foolproof config. >=20 > Yeah, to make it really trustworthy we would need to prevent > migration to hosts with mismatching phys sizes. Wouldn't it be sufficient to prevent guestphysbits > hostphysbits? > We would need to > communicate that to the guest somehow (with new hypervisor CPUID > flags, maybe). >=20 > --=20 > Eduardo --Apple-Mail=_12CD78C0-16CE-40CF-8F46-CE5829A775C8 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8

Le 16 Jun 202= 0 =C3=A0 19:10, Eduardo Habkost <ehabkost@redhat.com> a =C3=A9crit :

On Tue, Jun 16, 2020 at 05:5= 7:46PM +0100, Dr. David Alan Gilbert wrote:
* Gerd Hoffmann (kraxel@redhat.com) wrote:
 Hi,

(a) We could rely in the guest physbits to c= alculate the PCI64 aperture.

I'd = love to do that.  Move the 64-bit I/O window as high as possible anduse -- say -- 25% of the physical address space for it.

Problem is we can't.

failure. Also, if the users are not sett= ing the physbits in the guest,
there must be a default (seems= to be 40bit according to my experiments),
seems to be a good= idea to rely on that.

Yes, 40 is= the default, and it is used *even if the host supports less
= than that*.  Typical values I've seen for intel hardware are 36 and 39= .
39 is used even by recent hardware (not the xeons, but chec= k out a
laptop or a nuc).

If guest physbits is 40, why to have OVMF li= miting it to 36, right?

Things wi= ll explode in case OVMF uses more physbits than the host
supp= orts (host physbits limit applies to ept too).  In other words: OVMFcan't trust the guest physbits, so it is conservative to be on= the safe
side.

If we can someho= w make a *trustable* physbits value available to the
guest, t= hen yes, we can go that route.  But the guest physbits we have
today unfortunately don't cut it.

In downstream RH qemu, we run with host-physbits as default; so it'= s reasonably
trustworthy; of course that doesn't help you acr= oss a migration between
hosts with different sizes (e.g. an E= 5 Xeon to an E3).
Changing upstream to do the same would seem= sensible to me, but it's not
a foolproof config.

Yeah, to make= it really trustworthy we would need to prevent
migration to hosts with mismatching phys sizes.

Wouldn't it be suffic= ient to prevent guestphysbits > hostphysbits?

 We would need = to
communicate that to = the guest somehow (with new hypervisor CPUID
flags, maybe).

-- 
Eduardo

--Apple-Mail=_12CD78C0-16CE-40CF-8F46-CE5829A775C8--