From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaODD-0006lK-Tt for qemu-devel@nongnu.org; Mon, 29 Feb 2016 08:50:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aaODA-0001nu-0m for qemu-devel@nongnu.org; Mon, 29 Feb 2016 08:50:11 -0500 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:33694) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaOD9-0001nK-NF for qemu-devel@nongnu.org; Mon, 29 Feb 2016 08:50:07 -0500 Received: by mail-wm0-x230.google.com with SMTP id l68so37623341wml.0 for ; Mon, 29 Feb 2016 05:50:07 -0800 (PST) Sender: Paolo Bonzini References: <1456751763-24244-1-git-send-email-a.rigo@virtualopensystems.com> From: Paolo Bonzini Message-ID: <56D44C8C.3050800@redhat.com> Date: Mon, 29 Feb 2016 14:50:04 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [mttcg] cputlb: Use async tlb_flush_by_mmuidx List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Alvise Rigo Cc: mttcg@listserver.greensocs.com, Claudio Fontana , Mark Burton , QEMU Developers , Jani Kokkonen , "tech@virtualopensystems.com" , =?UTF-8?Q?Alex_Benn=c3=a9e?= , =?UTF-8?B?S09OUkFEIEZyw6lkw6lyaWM=?= On 29/02/2016 14:21, Peter Maydell wrote: > On 29 February 2016 at 13:16, Alvise Rigo wrote: >> > As in the case of tlb_flush(), also tlb_flush_by_mmuidx has to query the >> > TLB flush if it targets another VCPU. To accomplish this, a new async >> > work has been added, together with a new TLBFlushByMMUIdxParams. A >> > bitmap is used to track the MMU indexes to flush. >> > >> > This patch applies to the multi_tcg_v8 branch. > What's the API for a target CPU emulation to say "and now I must > wait for the TLB op to finish" before completing this guest > instruction? My proposal has been for a while for DMB to put the CPU in a halted state (remote TLB callbacks then can decrement a counter and signal cpu_halt_cond when it's zero), but no one has implemented this. Paolo