From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaQch-0007sv-NO for qemu-devel@nongnu.org; Mon, 29 Feb 2016 11:24:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aaQcg-0004Lk-Sb for qemu-devel@nongnu.org; Mon, 29 Feb 2016 11:24:39 -0500 References: <1456762734-23939-1-git-send-email-peter.maydell@linaro.org> From: Sergey Fedorov Message-ID: <56D470B9.3090609@gmail.com> Date: Mon, 29 Feb 2016 19:24:25 +0300 MIME-Version: 1.0 In-Reply-To: <1456762734-23939-1-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-arm: Implement MRS (banked) and MSR (banked) instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , qemu-arm@nongnu.org On 29.02.2016 19:18, Peter Maydell wrote: > Starting with the ARMv7 Virtualization Extensions, the A32 and T32 > instruction sets provide instructions "MSR (banked)" and "MRS > (banked)" which can be used to access registers for a mode other > than the current one: > * R_ > * ELR_hyp > * SPSR_ > > Implement the missing instructions. Likely, there is no disassembling support in QEMU for these instructions as well. Are you going to add it? Best regards, Sergey > > Signed-off-by: Peter Maydell > --- > We don't support EL2 yet, but you can get at these on a v8 CPU in > 32-bit EL1 if EL3 is enabled. Obviously there's not going to be much > 32-bit EL1 code out there that uses the insns though, as it wouldn't > work on v7 if it did...