From: Richard Henderson <rth@twiddle.net>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: hpoussin@reactos.org
Subject: Re: [Qemu-devel] [PATCH] target-i386: fix smsw and lmsw from/to register
Date: Tue, 1 Mar 2016 08:34:17 -0800 [thread overview]
Message-ID: <56D5C489.3060201@twiddle.net> (raw)
In-Reply-To: <1456845134-18812-1-git-send-email-pbonzini@redhat.com>
On 03/01/2016 07:12 AM, Paolo Bonzini wrote:
> SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386:
> Rearrange processing of 0F 01", 2016-02-13) did not account for that.
>
> Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1
> Cc: rth@twiddle.net
> Reported-by: Hervé Poussineau <hpoussin@reactos.org>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target-i386/translate.c | 38 ++++++++++++++++++++++----------------
> 1 file changed, 22 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
Sorry about that. As recompense, I just noticed that we're not implementing
these instructions properly for 64-bit mode. I'll post a patch for that as well.
r~
next prev parent reply other threads:[~2016-03-01 16:34 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 15:12 [Qemu-devel] [PATCH] target-i386: fix smsw and lmsw from/to register Paolo Bonzini
2016-03-01 16:34 ` Richard Henderson [this message]
2016-03-01 19:42 ` Hervé Poussineau
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