From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaoOA-0000wl-0C for qemu-devel@nongnu.org; Tue, 01 Mar 2016 12:47:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aaoN9-000079-0D for qemu-devel@nongnu.org; Tue, 01 Mar 2016 12:47:13 -0500 Received: from mail-qg0-x242.google.com ([2607:f8b0:400d:c04::242]:35486) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaoN8-00006u-QI for qemu-devel@nongnu.org; Tue, 01 Mar 2016 12:46:10 -0500 Received: by mail-qg0-x242.google.com with SMTP id p68so8329526qge.2 for ; Tue, 01 Mar 2016 09:46:10 -0800 (PST) Sender: Richard Henderson References: <1456849468-30217-1-git-send-email-kbastian@mail.uni-paderborn.de> <1456849468-30217-2-git-send-email-kbastian@mail.uni-paderborn.de> From: Richard Henderson Message-ID: <56D5D55F.3000406@twiddle.net> Date: Tue, 1 Mar 2016 09:46:07 -0800 MIME-Version: 1.0 In-Reply-To: <1456849468-30217-2-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/7] target-tricore: Add FPU infrastructure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org On 03/01/2016 08:24 AM, Bastian Koppelmann wrote: > +static inline void f_update_psw_flags(CPUTriCoreState *env, bool calc_z) You probably need it for compiling this intermediate patch, but probably drop inline and let the compiler choose. This is quite a bit of code after all... > +{ > + int8_t flags = env->fp_status.float_exception_flags; > + int32_t some_excp = 0; You need to set float_exception_flags to zero after reading, so that you don't re-copy the flags during the next fp insn. > +#define FPU_FS PSW_USB_C > +#define FPU_FI PSW_USB_V > +#define FPU_FV PSW_USB_SV > +#define FPU_FZ PSW_USB_AV > +#define FPU_FU PSW_USB_SAV What an unfortunate spec. This is an incredibly broken way to implement fp exception flags. Exception flags are the sort of thing that's supposed to be collected across a whole subroutine, without having to worry about the fp exception flags being clobbered by the surrounding pointer arithmetic. In order to implement proper IEEE support with this chip, one would have to implement the fp exception word in software, clearing the PSW bits before each group of fp instructions and storing the PSW bits after each such group. Oh well. You're doing what the manual says... r~