From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions
Date: Tue, 1 Mar 2016 10:10:52 -0800 [thread overview]
Message-ID: <56D5DB2C.4010801@twiddle.net> (raw)
In-Reply-To: <1456849468-30217-4-git-send-email-kbastian@mail.uni-paderborn.de>
> + f_set_flags(env); \
You shouldn't need to set the flags every instruction.
You ought to be able to limit the changes to reset and
stores to the PSW.
> + arg1 = float32_squash_input_denormal(arg1, &env->fp_status); \
> + arg2 = float32_squash_input_denormal(arg2, &env->fp_status); \
> + \
> + if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) { \
> + f_result = QUIET_NAN; \
> + if (float32_is_signaling_nan(arg1) || \
> + float32_is_signaling_nan(arg2)) { \
> + env->fp_status.float_exception_flags |= float_flag_invalid; \
> + } \
> + } else if (f_is_pos_inf(arg1) && f_is_neg_inf(arg2)) { \
> + f_result = ADD_NAN; \
> + } else if (f_is_pos_inf(arg2) && f_is_neg_inf(arg1)) { \
> + f_result = ADD_NAN; \
> + } else { \
> + f_result = float32_##name(arg1, arg2 , &env->fp_status); \
> + } \
If we assume that exceptional situations are, well, exceptional, then we can
re-order this to
f_result = float32_op(arg1, arg2, &env->fp_status);
flags = env->fp_status.float_exception_flags;
if (flags) {
/* If the output is a NaN, but the inputs aren't,
we return a unique value. */
if ((flags & float_flag_invalid)
&& !float32_is_any_nan(arg1)
&& !float32_is_any_nan(arg2)) {
f_result = ADD_NAN;
}
f_update_psw_flags(env, flags, false);
}
This does assume that fp_status.default_nan_mode = 1, so that
float32_default_nan is returned. Which means that first patch should touch
fpu/softfloat-specialize.h to add tricore to the list of those defaulting to
0x7fc00000.
r~
next prev parent reply other threads:[~2016-03-01 18:11 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 16:24 [Qemu-devel] [PATCH 0/7] TriCore FPU patches Bastian Koppelmann
2016-03-01 16:24 ` [Qemu-devel] [PATCH 1/7] target-tricore: Add FPU infrastructure Bastian Koppelmann
2016-03-01 17:46 ` Richard Henderson
2016-03-01 16:24 ` [Qemu-devel] [PATCH 2/7] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide Bastian Koppelmann
2016-03-01 17:46 ` Richard Henderson
2016-03-01 16:24 ` [Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions Bastian Koppelmann
2016-03-01 18:10 ` Richard Henderson [this message]
2016-03-01 16:24 ` [Qemu-devel] [PATCH 4/7] target-tricore: Add mul.f instruction Bastian Koppelmann
2016-03-01 16:24 ` [Qemu-devel] [PATCH 5/7] target-tricore: Add div.f instruction Bastian Koppelmann
2016-03-01 16:24 ` [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction Bastian Koppelmann
2016-03-01 18:21 ` Richard Henderson
2016-03-08 10:20 ` Bastian Koppelmann
2016-03-08 14:42 ` Richard Henderson
2016-03-08 15:07 ` Bastian Koppelmann
2016-03-08 15:11 ` Bastian Koppelmann
2016-03-08 15:37 ` Richard Henderson
2016-03-08 15:40 ` Bastian Koppelmann
2016-03-01 16:24 ` [Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions Bastian Koppelmann
2016-03-01 18:26 ` Richard Henderson
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