From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaolB-00067F-4G for qemu-devel@nongnu.org; Tue, 01 Mar 2016 13:11:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aaol6-0008Ld-1Z for qemu-devel@nongnu.org; Tue, 01 Mar 2016 13:11:01 -0500 Received: from mail-qg0-x243.google.com ([2607:f8b0:400d:c04::243]:33394) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aaol5-0008LV-TS for qemu-devel@nongnu.org; Tue, 01 Mar 2016 13:10:55 -0500 Received: by mail-qg0-x243.google.com with SMTP id y89so13053228qge.0 for ; Tue, 01 Mar 2016 10:10:55 -0800 (PST) Sender: Richard Henderson References: <1456849468-30217-1-git-send-email-kbastian@mail.uni-paderborn.de> <1456849468-30217-4-git-send-email-kbastian@mail.uni-paderborn.de> From: Richard Henderson Message-ID: <56D5DB2C.4010801@twiddle.net> Date: Tue, 1 Mar 2016 10:10:52 -0800 MIME-Version: 1.0 In-Reply-To: <1456849468-30217-4-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org > + f_set_flags(env); \ You shouldn't need to set the flags every instruction. You ought to be able to limit the changes to reset and stores to the PSW. > + arg1 = float32_squash_input_denormal(arg1, &env->fp_status); \ > + arg2 = float32_squash_input_denormal(arg2, &env->fp_status); \ > + \ > + if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) { \ > + f_result = QUIET_NAN; \ > + if (float32_is_signaling_nan(arg1) || \ > + float32_is_signaling_nan(arg2)) { \ > + env->fp_status.float_exception_flags |= float_flag_invalid; \ > + } \ > + } else if (f_is_pos_inf(arg1) && f_is_neg_inf(arg2)) { \ > + f_result = ADD_NAN; \ > + } else if (f_is_pos_inf(arg2) && f_is_neg_inf(arg1)) { \ > + f_result = ADD_NAN; \ > + } else { \ > + f_result = float32_##name(arg1, arg2 , &env->fp_status); \ > + } \ If we assume that exceptional situations are, well, exceptional, then we can re-order this to f_result = float32_op(arg1, arg2, &env->fp_status); flags = env->fp_status.float_exception_flags; if (flags) { /* If the output is a NaN, but the inputs aren't, we return a unique value. */ if ((flags & float_flag_invalid) && !float32_is_any_nan(arg1) && !float32_is_any_nan(arg2)) { f_result = ADD_NAN; } f_update_psw_flags(env, flags, false); } This does assume that fp_status.default_nan_mode = 1, so that float32_default_nan is returned. Which means that first patch should touch fpu/softfloat-specialize.h to add tricore to the list of those defaulting to 0x7fc00000. r~