From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ab8nB-0002PQ-AA for qemu-devel@nongnu.org; Wed, 02 Mar 2016 10:34:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ab8n7-0006Yx-7X for qemu-devel@nongnu.org; Wed, 02 Mar 2016 10:34:25 -0500 Received: from mx1.redhat.com ([209.132.183.28]:50610) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ab8n7-0006Yl-2J for qemu-devel@nongnu.org; Wed, 02 Mar 2016 10:34:21 -0500 References: <1456856919-32447-1-git-send-email-rth@twiddle.net> From: Paolo Bonzini Message-ID: <56D707F8.8070804@redhat.com> Date: Wed, 2 Mar 2016 16:34:16 +0100 MIME-Version: 1.0 In-Reply-To: <1456856919-32447-1-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-i386: Fix SMSW for 64-bit mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org On 01/03/2016 19:28, Richard Henderson wrote: > In non-64-bit modes, the instruction always stores 16 bits. > But in 64-bit mode, when the destination is a register, the > instruction can write 32 or 64 bits. > > Signed-off-by: Richard Henderson > --- > target-i386/translate.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/target-i386/translate.c b/target-i386/translate.c > index 1413069..482e93a 100644 > --- a/target-i386/translate.c > +++ b/target-i386/translate.c > @@ -7282,12 +7282,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, > > CASE_MODRM_OP(4): /* smsw */ > gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); > -#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN > - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) + 4); > -#else > - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); > -#endif > - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); > + tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); > + if (CODE64(s)) { > + mod = (modrm >> 6) & 3; > + ot = (mod != 3 ? MO_16 : s->dflag); > + } else { > + ot = MO_16; > + } > + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); > break; > > CASE_MODRM_OP(6): /* lmsw */ > Thanks, queued together with the modrm=3 fix. Paolo