From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:39683)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <digetx@gmail.com>) id 1aftUB-0006Kt-PH
	for qemu-devel@nongnu.org; Tue, 15 Mar 2016 14:14:28 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <digetx@gmail.com>) id 1aftUA-0005te-SQ
	for qemu-devel@nongnu.org; Tue, 15 Mar 2016 14:14:27 -0400
References: <1457928832-31026-1-git-send-email-andrew@aj.id.au>
	<1457928832-31026-2-git-send-email-andrew@aj.id.au>
From: Dmitry Osipenko <digetx@gmail.com>
Message-ID: <56E850F9.5080307@gmail.com>
Date: Tue, 15 Mar 2016 21:14:17 +0300
MIME-Version: 1.0
In-Reply-To: <1457928832-31026-2-git-send-email-andrew@aj.id.au>
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Subject: Re: [Qemu-devel] [PATCH v4 1/4] hw/timer: Add ASPEED timer device
	model
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Andrew Jeffery <andrew@aj.id.au>, Peter Maydell <peter.maydell@linaro.org>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>, Jeremy Kerr <jk@ozlabs.org>, qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= <clg@kaod.org>

Hello Andrew,

14.03.2016 07:13, Andrew Jeffery пишет:
> Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to
> 8 timers can independently be configured, enabled, reset and disabled.
> Some hardware features are not implemented, namely clock value matching
> and pulse generation, but the implementation is enough to boot the Linux
> kernel configured with aspeed_defconfig.
>

[snip]

> +static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
> +                                   uint32_t value)
> +{
> +    AspeedTimer *t;
> +
> +    g_assert(timer >= 0 && timer < ASPEED_TIMER_NR_TIMERS);

This would never fail, wouldn't it?

[snip]

> +static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value,
> +                               unsigned size)
> +{
> +    const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
> +    const int reg = (offset & 0xf) / 4;
> +    AspeedTimerCtrlState *s = opaque;
> +
> +    switch (offset) {
> +    /* Control Registers */
> +    case 0x30:
> +        aspeed_timer_set_ctrl(s, tv);
> +        break;
> +    case 0x34:
> +        aspeed_timer_set_ctrl2(s, tv);
> +        break;
> +    /* Timer Registers */
> +    case 0x00 ... 0x2c:
> +        aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv);
> +        break;
> +    case 0x40 ... 0x8c:
> +        aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv);
> +        break;


[snip]

> +static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)
> +{
> +    QEMUBH *bh;
> +    AspeedTimer *t = &s->timers[id];
> +
> +    t->id = id;
> +    bh = qemu_bh_new(aspeed_timer_expire, t);
> +    assert(bh);
> +    t->timer = ptimer_init(bh);
> +    assert(t->timer);
> +}

I'm wondering why do you need those asserts, it's very unlikely that this code 
would fail. Have you had any weird issues with it?

-- 
Dmitry