From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1agFXC-0002pz-K6 for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:47:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1agFX7-0001n1-JF for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:47:02 -0400 References: <1458134034-32500-1-git-send-email-clg@fr.ibm.com> <1458134034-32500-9-git-send-email-clg@fr.ibm.com> From: Thomas Huth Message-ID: <56E99C0D.5050509@redhat.com> Date: Wed, 16 Mar 2016 18:46:53 +0100 MIME-Version: 1.0 In-Reply-To: <1458134034-32500-9-git-send-email-clg@fr.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 08/10] ppc: Add POWER8 IAMR register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 16.03.2016 14:13, C=C3=A9dric Le Goater wrote: > From: Benjamin Herrenschmidt >=20 > With appropriate AMR-like masks. Not actually used by the translation > logic at that point >=20 > Signed-off-by: Benjamin Herrenschmidt > [clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR= ) > changed gen_spr_amr() prototype ] > Signed-off-by: C=C3=A9dric Le Goater > --- > target-ppc/cpu.h | 1 + > target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++= ++-- > 2 files changed, 40 insertions(+), 2 deletions(-) >=20 > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 167c73f863b3..a3c4fb112a3e 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1360,6 +1360,7 @@ static inline int cpu_mmu_index (CPUPPCState *env= , bool ifetch) > #define SPR_BOOKE_CSRR0 (0x03A) > #define SPR_BOOKE_CSRR1 (0x03B) > #define SPR_BOOKE_DEAR (0x03D) > +#define SPR_IAMR (0x03D) > #define SPR_BOOKE_ESR (0x03E) > #define SPR_BOOKE_IVPR (0x03F) > #define SPR_MPC_EIE (0x050) > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 4514188ff07c..c78b532e8f3c 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -1126,9 +1126,39 @@ static void spr_write_uamor(DisasContext *ctx, i= nt sprn, int gprn) > tcg_temp_free(t1); > tcg_temp_free(t2); > } > + > +static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) > +{ > + TCGv t0 =3D tcg_temp_new(); > + TCGv t1 =3D tcg_temp_new(); > + TCGv t2 =3D tcg_temp_new(); > + > + /* Note, the HV=3D1 case is handled earlier by simply using > + * spr_write_generic for HV mode in the SPR table > + */ > + > + /* Build insertion mask into t1 based on context */ > + gen_load_spr(t1, SPR_AMOR); > + > + /* Mask new bits into t2 */ > + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); > + > + /* Load AMR and clear new bits in t0 */ > + gen_load_spr(t0, SPR_IAMR); > + tcg_gen_andc_tl(t0, t0, t1); > + > + /* Or'in new bits and write it out */ > + tcg_gen_or_tl(t0, t0, t2); > + gen_store_spr(SPR_IAMR, t0); > + spr_store_dump_spr(SPR_IAMR); > + > + tcg_temp_free(t0); > + tcg_temp_free(t1); > + tcg_temp_free(t2); > +} > #endif /* CONFIG_USER_ONLY */ > =20 > -static void gen_spr_amr (CPUPPCState *env) > +static void gen_spr_amr(CPUPPCState *env, bool has_iamr) > { > #ifndef CONFIG_USER_ONLY > /* Virtual Page Class Key protection */ > @@ -1154,6 +1184,13 @@ static void gen_spr_amr (CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0); > + if (!has_iamr) { > + spr_register_kvm_hv(env, SPR_IAMR, "IAMR", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_iamr, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_IAMR, 0); > + } That should be now a "if (has_iamr)" instead of "if (!has_iamr)", shouldn't it? Thomas