From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alQs7-00016K-5b for qemu-devel@nongnu.org; Wed, 30 Mar 2016 20:54:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alQs3-0002g1-VQ for qemu-devel@nongnu.org; Wed, 30 Mar 2016 20:54:03 -0400 References: <1459357980-29330-1-git-send-email-lvivier@redhat.com> <20160331102945.5a31dbe5@voom.fritz.box> From: Laurent Vivier Message-ID: <56FC7522.1080207@redhat.com> Date: Thu, 31 Mar 2016 02:53:54 +0200 MIME-Version: 1.0 In-Reply-To: <20160331102945.5a31dbe5@voom.fritz.box> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: thuth@redhat.com, qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org On 31/03/2016 01:29, David Gibson wrote: > On Wed, 30 Mar 2016 19:13:00 +0200 > Laurent Vivier wrote: >=20 >> If the processor is in little-endian mode, an alignment interrupt must >> occur for the following instructions: lmw, stmw, lswi, lswx, stswi or = stswx. >> >> This is what happens with KVM, so change TCG to do the same. >> >> As the instruction can be emulated by the kernel, enable the change >> only in softmmu mode. >> >> Signed-off-by: Laurent Vivier >=20 > I guess this makes sense given the existing hardware behaviour, even > though it seems a bit perverse to me to make the emulator strictly less > functional. >=20 > Alex, what do you think? >=20 > Note that in time I expect we'll want some new flag to control this > behaviour. Given the push towards LE, I think it's pretty likely that > future CPUs (maybe even POWER9) will allow these operations on LE > without exceptions. >=20 > I guess one question here is what does the architecture say about > this? Does it say these operations will generate alignment exceptions > on LE, or just that they may (implementation dependent)? "Power ISA Version 2.07 Book III-S 6.5.8 Alignment Interrupt An Alignment interrupt occurs when no higher priority exception exists and a data access cannot be per- formed for any of the following reasons. ... * The instruction is lmw, stmw, lswi, lswx, stswi, or stswx, and the operand is in storage that is Write Through Required or Caching Inhibited, or the thread is in Little-Endian mode. ..." And this is very similar in "The PowerPC Architecture, A specification for a new family of risc processors Book III PowerPC Operating Environment Architecture 5.5.6 Alignment Interrupt An Alignment interrupt occurs when no higher priority exception exists and the implementation cannot perform a storage access for one of the reasons listed below. ... * The instruction is lmw, stmw, lswi, lswx, stswi, or stswx, and the processor is in Little-Endian mode. ..." And "Power ISA version 3.0" Chapter 3. Fixed-Point Facility ... lswi ... This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode, the system alignment error handler is invoked. ... Book III 6.5.8 Alignment Interrupt ... An Alignment interrupt occurs when no higher priority exception exists and an attempt is made to execute an instruction in a manner that is required, by the instruction description, to cause an Alignment interrupt. These cases are as follows. =C2=84* A Load/Store Multiple instruction that is executed in Little-Endian mode ... An Alignment interrupt may occur when no higher priority exception exists and a data access cannot be performed for any of the following reasons ..." Laurent