From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alXCq-0005DN-32 for qemu-devel@nongnu.org; Thu, 31 Mar 2016 03:39:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alXCj-00012F-Tk for qemu-devel@nongnu.org; Thu, 31 Mar 2016 03:39:52 -0400 References: <1459357980-29330-1-git-send-email-lvivier@redhat.com> <20160331102945.5a31dbe5@voom.fritz.box> <56FCC99C.2030809@suse.de> <56FCCC6A.7000002@redhat.com> <56FCCEA3.5030705@suse.de> From: Laurent Vivier Message-ID: <56FCD43D.8000004@redhat.com> Date: Thu, 31 Mar 2016 09:39:41 +0200 MIME-Version: 1.0 In-Reply-To: <56FCCEA3.5030705@suse.de> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf , David Gibson Cc: thuth@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 31/03/2016 09:15, Alexander Graf wrote: > > > On 31.03.16 09:06, Laurent Vivier wrote: >> >> >> On 31/03/2016 08:54, Alexander Graf wrote: >>> >>> >>> On 31.03.16 01:29, David Gibson wrote: >>>> On Wed, 30 Mar 2016 19:13:00 +0200 >>>> Laurent Vivier wrote: >>>> >>>>> If the processor is in little-endian mode, an alignment interrupt must >>>>> occur for the following instructions: lmw, stmw, lswi, lswx, stswi or stswx. >>>>> >>>>> This is what happens with KVM, so change TCG to do the same. >>>>> >>>>> As the instruction can be emulated by the kernel, enable the change >>>>> only in softmmu mode. >>>>> >>>>> Signed-off-by: Laurent Vivier >>>> >>>> I guess this makes sense given the existing hardware behaviour, even >>>> though it seems a bit perverse to me to make the emulator strictly less >>>> functional. >>>> >>>> Alex, what do you think? >>> >>> In general we only implement strict checks if it breaks guests not to >>> have them. Are you aware of any such case? >> >> No, it does not break anything. The idea was to have the same behavior >> with TCG as with a real CPU (or kvm). But if it is not the rule, we can >> drop this patch. > > I guess if you really care about same behavior, we'd need to have risu > ported to ppc. However, that's a huge can of worms. Once we start that, > we'd have to verify risu against every single CPU type we support > because they all interpret certain corner cases differently. I didn't know risu: it seems to be a wonderful tool! > > That's basically what David was trying to say with POWER9. How do you > know that POWER9 still requires strong alignment checks for indexed LE > instructions? If it doesn't, we'd have to add a case in TCG to not the > the checks again. These multiply very quickly :). I understand. So just forget this patch :) Thanks, Laurent