From: Alexander Graf <agraf@suse.de>
To: Thomas Huth <thuth@redhat.com>,
Laurent Vivier <lvivier@redhat.com>,
David Gibson <dgibson@redhat.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception
Date: Thu, 31 Mar 2016 11:03:10 +0200 [thread overview]
Message-ID: <56FCE7CE.10702@suse.de> (raw)
In-Reply-To: <56FCE4C5.1040706@redhat.com>
On 03/31/2016 10:50 AM, Thomas Huth wrote:
> On 31.03.2016 09:15, Alexander Graf wrote:
>> On 31.03.16 09:06, Laurent Vivier wrote:
>>> On 31/03/2016 08:54, Alexander Graf wrote:
>>>> On 31.03.16 01:29, David Gibson wrote:
>>>>> On Wed, 30 Mar 2016 19:13:00 +0200
>>>>> Laurent Vivier <lvivier@redhat.com> wrote:
>>>>>
>>>>>> If the processor is in little-endian mode, an alignment interrupt must
>>>>>> occur for the following instructions: lmw, stmw, lswi, lswx, stswi or stswx.
>>>>>>
>>>>>> This is what happens with KVM, so change TCG to do the same.
>>>>>>
>>>>>> As the instruction can be emulated by the kernel, enable the change
>>>>>> only in softmmu mode.
>>>>>>
>>>>>> Signed-off-by: Laurent Vivier <lvivier@redhat.com>
>>>>> I guess this makes sense given the existing hardware behaviour, even
>>>>> though it seems a bit perverse to me to make the emulator strictly less
>>>>> functional.
>>>>>
>>>>> Alex, what do you think?
>>>> In general we only implement strict checks if it breaks guests not to
>>>> have them. Are you aware of any such case?
> Well, the new "emulator" test for kvm-unit-tests only works right if
> this is done correctly ;-)
>
>> That's basically what David was trying to say with POWER9. How do you
>> know that POWER9 still requires strong alignment checks for indexed LE
>> instructions? If it doesn't, we'd have to add a case in TCG to not the
>> the checks again. These multiply very quickly :).
> I'd agree with you in case something is not properly defined in the ISA
> or marked as implementation specific. But in this case, this behavior is
> properly documented in the PowerISA spec. IMHO, if something is
> documented in the ISA, we should follow that behavior in QEMU, too, i.e.
It's not even necessarily about documented or not. It's about
differences in different PowerISA versions :).
> add the alignment checks here. And if POWER9 is different, there must be
> a new version of the PowerISA for this one day ... i.e. we have to make
> adaptions for that anyway.
Yup, and the less we have to adapt the happier everyone is.
But if it makes the emulator test work, I'm fine with it. Again, safety
checks should have a real world impact.
Alex
next prev parent reply other threads:[~2016-03-31 9:03 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 17:13 [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception Laurent Vivier
2016-03-30 23:29 ` David Gibson
2016-03-31 0:53 ` Laurent Vivier
2016-03-31 6:54 ` Alexander Graf
2016-03-31 7:06 ` Laurent Vivier
2016-03-31 7:15 ` Alexander Graf
2016-03-31 7:39 ` Laurent Vivier
2016-03-31 8:50 ` Thomas Huth
2016-03-31 9:03 ` Alexander Graf [this message]
2016-03-31 9:18 ` Thomas Huth
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