Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception

[Thomas Huth <thuth@redhat.com>]

On 31.03.2016 11:03, Alexander Graf wrote:
> On 03/31/2016 10:50 AM, Thomas Huth wrote:
>> On 31.03.2016 09:15, Alexander Graf wrote:
>>> On 31.03.16 09:06, Laurent Vivier wrote:
>>>> On 31/03/2016 08:54, Alexander Graf wrote:
>>>>> On 31.03.16 01:29, David Gibson wrote:
>>>>>> On Wed, 30 Mar 2016 19:13:00 +0200
>>>>>> Laurent Vivier <lvivier@redhat.com> wrote:
>>>>>>
>>>>>>> If the processor is in little-endian mode, an alignment interrupt
>>>>>>> must
>>>>>>> occur for the following instructions: lmw, stmw, lswi, lswx,
>>>>>>> stswi or stswx.
>>>>>>>
>>>>>>> This is what happens with KVM, so change TCG to do the same.
>>>>>>>
>>>>>>> As the instruction can be emulated by the kernel, enable the change
>>>>>>> only in softmmu mode.
>>>>>>>
>>>>>>> Signed-off-by: Laurent Vivier <lvivier@redhat.com>
>>>>>> I guess this makes sense given the existing hardware behaviour, even
>>>>>> though it seems a bit perverse to me to make the emulator strictly
>>>>>> less
>>>>>> functional.
>>>>>>
>>>>>> Alex, what do you think?
>>>>> In general we only implement strict checks if it breaks guests not to
>>>>> have them. Are you aware of any such case?
>> Well, the new "emulator" test for kvm-unit-tests only works right if
>> this is done correctly ;-)
>>
>>> That's basically what David was trying to say with POWER9. How do you
>>> know that POWER9 still requires strong alignment checks for indexed LE
>>> instructions? If it doesn't, we'd have to add a case in TCG to not the
>>> the checks again. These multiply very quickly :).
>> I'd agree with you in case something is not properly defined in the ISA
>> or marked as implementation specific. But in this case, this behavior is
>> properly documented in the PowerISA spec. IMHO, if something is
>> documented in the ISA, we should follow that behavior in QEMU, too, i.e.
> 
> It's not even necessarily about documented or not. It's about
> differences in different PowerISA versions :).

As Laurent already mentioned it in another mail, it's defined like this
in pretty much all of the ISAs - at least from 2.01 to 2.07 as far as I
can see, too. (I don't have an older version of the PowerISA than 2.01).
I just checked also the "User Manuals" of the PPC 601, the PPC 603, and
the MPC750, and they also specify that these instructions cause an
alignment exception in little endian mode, so I think this really should
occur pretty much with every PPC chip that can run in little endian mode.

 Thomas