From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aliiF-00031H-0l for qemu-devel@nongnu.org; Thu, 31 Mar 2016 15:57:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alii8-0003Hb-C9 for qemu-devel@nongnu.org; Thu, 31 Mar 2016 15:57:02 -0400 Received: from mail-wm0-x22a.google.com ([2a00:1450:400c:c09::22a]:35472) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alii8-0003HQ-4t for qemu-devel@nongnu.org; Thu, 31 Mar 2016 15:56:56 -0400 Received: by mail-wm0-x22a.google.com with SMTP id 191so138007436wmq.0 for ; Thu, 31 Mar 2016 12:56:55 -0700 (PDT) Sender: Paolo Bonzini References: <56FC0818.10002@linaro.org> <56FC174A.6070906@redhat.com> <56FD22A5.10501@gmail.com> <87wpoig44r.fsf@linaro.org> <56FD2EFB.3060302@gmail.com> <56FD7486.20707@gmail.com> From: Paolo Bonzini Message-ID: <56FD8102.6050203@redhat.com> Date: Thu, 31 Mar 2016 21:56:50 +0200 MIME-Version: 1.0 In-Reply-To: <56FD7486.20707@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] tcg: reworking tb_invalidated_flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: Richard Henderson , QEMU Developers , Sergey Fedorov , Peter Crosthwaite On 31/03/2016 21:03, Sergey Fedorov wrote: > Looks like we have to ensure all vCPUs are out of translated code when > doing TB patching either doing tb_add_jump() or tb_phys_invalidate(). > Did I missed something? Almost all TCG targets have naturally aligned instructions, so that's not a problem; we can assume that 32-bit writes are atomic, though perhaps we can change them to atomic_set just to be safe. Only s390 and x86 can have unaligned instructions. For x86 I suppose you can use 1 to 3 byte nops so that the first byte of the jump ends up at ip%4=3. For s390 you can do the same, I don't know the encoding of the canonical nop but an "or 0,0" instruction can do and is 16 bits wide (in this case instructions are 16-bit aligned so you'd want ip%4=2). Paolo