From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am4M6-0001GJ-By for qemu-devel@nongnu.org; Fri, 01 Apr 2016 15:03:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1am4M5-0004pw-Is for qemu-devel@nongnu.org; Fri, 01 Apr 2016 15:03:38 -0400 References: <1458910214-12239-1-git-send-email-aleksandar.markovic@rt-rk.com> <1458910214-12239-2-git-send-email-aleksandar.markovic@rt-rk.com> From: Leon Alrae Message-ID: <56FEC5D1.8020908@imgtec.com> Date: Fri, 1 Apr 2016 20:02:41 +0100 MIME-Version: 1.0 In-Reply-To: <1458910214-12239-2-git-send-email-aleksandar.markovic@rt-rk.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aleksandar Markovic , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, ehabkost@redhat.com, proljc@gmail.com, mark.cave-ayland@ilande.co.uk, agraf@suse.de, kbastian@mail.uni-paderborn.de, petar.jovanovic@imgtec.com, blauwirbel@gmail.com, jcmvbkbc@gmail.com, miodrag.dinic@imgtec.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, edgar.iglesias@gmail.com, pbonzini@redhat.com, gxt@mprc.pku.edu.cn, afaerber@suse.de, aurelien@aurel32.net, rth@twiddle.net On 25/03/16 12:50, Aleksandar Markovic wrote: > /*---------------------------------------------------------------------------- > | The pattern for a default generated single-precision NaN. > *----------------------------------------------------------------------------*/ > +float32 float32_default_nan(float_status *status) { > #if defined(TARGET_SPARC) > -const float32 float32_default_nan = const_float32(0x7FFFFFFF); > + return const_float32(0x7FFFFFFF); > #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ > defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE) > -const float32 float32_default_nan = const_float32(0x7FC00000); > -#elif SNAN_BIT_IS_ONE > -const float32 float32_default_nan = const_float32(0x7FBFFFFF); > + return const_float32(0x7FC00000); > #else > -const float32 float32_default_nan = const_float32(0xFFC00000); > + if (status->snan_bit_is_one) > + return const_float32(0x7FBFFFFF); > + else > + return const_float32(0xFFC00000); Here for MIPS (when FCR31.NAN2008 is set) we should generate 0x7FC00000 for single-precision. Reference: "MIPS Architecture For Programmers, Volume I-A: Introduction to the MIPS64 Architecture", Imagination Technologies LTD., Document Number: MD00083, Revision 6.01, August 20, 2014, Table 6.3 "Value Supplied When a New Quiet NaN Is Created", p. 84 Also, for double-precision we should generate 0x7FF8000000000000. Thanks, Leon