From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1an5xd-0004ig-KQ for qemu-devel@nongnu.org; Mon, 04 Apr 2016 10:58:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1an5xa-000126-FH for qemu-devel@nongnu.org; Mon, 04 Apr 2016 10:58:37 -0400 Received: from mail-lb0-x22a.google.com ([2a00:1450:4010:c04::22a]:36525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1an5xa-00011C-7x for qemu-devel@nongnu.org; Mon, 04 Apr 2016 10:58:34 -0400 Received: by mail-lb0-x22a.google.com with SMTP id qe11so164714435lbc.3 for ; Mon, 04 Apr 2016 07:58:33 -0700 (PDT) References: <1459435778-5526-1-git-send-email-peter.maydell@linaro.org> <1459435778-5526-5-git-send-email-peter.maydell@linaro.org> From: Sergey Fedorov Message-ID: <57028117.5090008@linaro.org> Date: Mon, 4 Apr 2016 17:58:31 +0300 MIME-Version: 1.0 In-Reply-To: <1459435778-5526-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: Avoid unnecessary TLB flush on TCR_EL2 writes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" On 31/03/16 17:49, Peter Maydell wrote: > The TCR_EL2 regdef was incorrectly using the vmsa_tcr_el1_write > function for writes. Since TCR_EL2 doesn't have the A1 bit that > TCR_EL1 does, we don't need to do a tlb_flush() when it is written. > Remove the unnecessary .writefn and also the harmless but unneeded > .raw_writefn and .resetfn definitions. How about TCR_EL3 which doesn't have A1 bit as well? Kind regards, Sergey > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 09638b2..4dbd844 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3559,8 +3559,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0 }, > { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, > - .access = PL2_RW, .writefn = vmsa_tcr_el1_write, > - .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, > + .access = PL2_RW, > + /* no .writefn needed as this can't cause an ASID change; > + * no .raw_writefn or .resetfn needed as we never use mask/base_mask > + */ > .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, > { .name = "VTCR", .state = ARM_CP_STATE_AA32, > .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,