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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id b3sm7492159oie.49.2020.10.09.15.34.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Oct 2020 15:34:05 -0700 (PDT) Subject: Re: [PATCH] target/arm: Fix SMLAD incorrect setting of Q bit To: Peter Maydell References: <20201009144712.11187-1-peter.maydell@linaro.org> <9b6bcfac-922d-675c-d7b4-35491a3efe60@linaro.org> From: Richard Henderson Message-ID: <5702c321-0d70-6e26-4aea-8ac9e6f90cbc@linaro.org> Date: Fri, 9 Oct 2020 17:34:02 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x243.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.208, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/9/20 1:47 PM, Peter Maydell wrote: > On Fri, 9 Oct 2020 at 18:57, Richard Henderson > wrote: >> >> On 10/9/20 9:47 AM, Peter Maydell wrote: >>> + /* >>> + * t1 is the low half of the result which goes into Rd. >>> + * We have overflow and must set Q if the high half (t2) >>> + * is different from the sign-extension of t1. >>> + */ >>> + t3 = tcg_temp_new_i32(); >>> + tcg_gen_sari_i32(t3, t1, 31); >>> + qf = load_cpu_field(QF); >>> + one = tcg_const_i32(1); >>> + tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf); >>> + store_cpu_field(qf, QF); >> >> This works, however, QF is not restricted to {0,1}. > > I'm not sure if you mean "this code doesn't maintain that > invariant" or "there is no such invariant". If the former, > the declaration of the field in cpu.h disagrees: > uint32_t QF; /* 0 or 1 */ Oops, I confused QF with QC, the neon saturation bit. r~