From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1anrTD-0007ch-Ex for qemu-devel@nongnu.org; Wed, 06 Apr 2016 13:42:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1anrT9-0001RV-Ef for qemu-devel@nongnu.org; Wed, 06 Apr 2016 13:42:23 -0400 Received: from mail-qg0-x242.google.com ([2607:f8b0:400d:c04::242]:35242) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1anrT9-0001RL-AO for qemu-devel@nongnu.org; Wed, 06 Apr 2016 13:42:19 -0400 Received: by mail-qg0-x242.google.com with SMTP id b32so4953456qgf.2 for ; Wed, 06 Apr 2016 10:42:19 -0700 (PDT) Sender: Richard Henderson References: <1459834253-8291-1-git-send-email-cota@braap.org> <1459834253-8291-8-git-send-email-cota@braap.org> <5703DCB7.50302@twiddle.net> <5703F3B4.6030108@twiddle.net> <20160406173255.GA27512@flamenco> From: Richard Henderson Message-ID: <57054A76.4080503@twiddle.net> Date: Wed, 6 Apr 2016 10:42:14 -0700 MIME-Version: 1.0 In-Reply-To: <20160406173255.GA27512@flamenco> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 07/10] tb hash: hash phys_pc, pc, and flags with xxhash List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Emilio G. Cota" , Laurent Desnogues Cc: MTTCG Devel , Peter Maydell , Peter Crosthwaite , QEMU Developers , Paolo Bonzini , Sergey Fedorov , =?UTF-8?Q?Alex_Benn=c3=a9e?= On 04/06/2016 10:32 AM, Emilio G. Cota wrote: > On Wed, Apr 06, 2016 at 08:06:57 +0200, Laurent Desnogues wrote: >> On Tue, Apr 5, 2016 at 7:19 PM, Richard Henderson wrote: >>> On 04/05/2016 09:33 AM, Laurent Desnogues wrote: >>>> The 'flags' field is 64-bit. You're thinking of cflags, I guess. >>> >>> Well that's silly. Since it's filled in via >>> >>> static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, >>> target_ulong *cs_base, int *flags) >>> >>> and passed back in to generate code with >>> >>> TranslationBlock *tb_gen_code(CPUState *cpu, >>> target_ulong pc, target_ulong cs_base, int flags, >>> int cflags); >>> >>> So while TranslationBlock stores "uint64_t", the producer and consumer see "int". >> >> I agree. I guess TranslationBlock should be fixed to use uint32_t >> (note several functions have to be changed from using int to uint32_t >> or aarch64-softmmu will fail). > > Can you please elaborate on this? The arm port is using some high bits, including #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) So, I would certainly be ok switching everything to use uint32_t over int. r~