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From: Tom Hanson <thomas.hanson@linaro.org>
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Date: Wed, 13 Apr 2016 07:36:15 -0600
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Subject: Re: [Qemu-devel] best way to implement emulation of AArch64 tagged
 addresses
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To: Richard Henderson <rth@twiddle.net>
Cc: Peter Maydell <peter.maydell@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>

On 04/11/2016 06:58 AM, Thomas Hanson wrote:
> Ah, true.
>
> On 9 April 2016 at 09:57, Richard Henderson <rth@twiddle.net
> <mailto:rth@twiddle.net>> wrote:
>
>     On 04/08/2016 05:29 PM, Thomas Hanson wrote:
>
>         Looking at tcg_out_tlb_load():
>         If I'm reading the pseudo-assembler of the function names
>         correctly, it looks
>         like in the i386 code we're already masking the address being
>         checked:
>               tgen_arithi(s, ARITH_AND + trexw, r1, TARGET_PAGE_MASK |
>         (aligned ? s_mask
>         : 0), 0);
>         where  TARGET_PAGE_MASK is a simple all-1's mask in the
>         appropriate upper bits.
>
>         Can we just poke some 0's into that mask in the tag locations?
>
>
>     No, because we'd no longer have a sign-extended 32-bit value, as
>     fits in that immediate operand field.  To load the constant you're
>     asking for, we'd need a 64-bit move insn and another register.
>
>
>     r~
>
>
[Sorry for the previous top post(s).  I've switched email clients...]

So, is the consensus that it's not worth adding an instruction to the 
fast path to avoid kicking out TLB entries with non-matching tags?

Or is this still under consideration?