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From: "Cédric Le Goater" <clg@kaod.org>
To: Kane Chen <kane_chen@aspeedtech.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Steven Lee <steven_lee@aspeedtech.com>,
	Troy Lee <leetroy@gmail.com>,
	Jamin Lin <jamin_lin@aspeedtech.com>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	Joel Stanley <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <troy_lee@aspeedtech.com>
Subject: Re: [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
Date: Fri, 7 Nov 2025 14:08:24 +0100	[thread overview]
Message-ID: <570ec70e-1f00-4649-9cd4-fa3e8acab251@kaod.org> (raw)
In-Reply-To: <20251105035859.3709907-3-kane_chen@aspeedtech.com>

On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> 
> Connect the LTPI controller device (representing the AST1700 I/O
> expander) to the AST27X0 SoC model. This patch sets up the memory
> mapping and device registration according to the AST2700 SoC design,
> where the LTPI controller is exposed at fixed MMIO regions.
> 
> This change only handles device instantiation and integration,
> without implementing the controller's internal logic.
> 
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
>   include/hw/arm/aspeed_soc.h |  5 +++++
>   hw/arm/aspeed_ast27x0.c     | 18 ++++++++++++++++++
>   2 files changed, 23 insertions(+)
> 
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 4b8e599f1a..bae60d85ea 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -42,6 +42,7 @@
>   #include "hw/fsi/aspeed_apb2opb.h"
>   #include "hw/char/serial-mm.h"
>   #include "hw/intc/arm_gicv3.h"
> +#include "hw/misc/aspeed_ltpi.h"
>   
>   #define VBOOTROM_FILE_NAME  "ast27x0_bootrom.bin"
>   
> @@ -53,6 +54,7 @@
>   #define ASPEED_UARTS_NUM 13
>   #define ASPEED_JTAG_NUM  2
>   #define ASPEED_PCIE_NUM  3
> +#define ASPEED_IOEXP_NUM 2
>   
>   struct AspeedSoCState {
>       DeviceState parent;
> @@ -110,6 +112,7 @@ struct AspeedSoCState {
>       UnimplementedDeviceState ltpi;
>       UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
>       AspeedAPB2OPBState fsi[2];
> +    AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
>   };
>   
>   #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -275,6 +278,8 @@ enum {
>       ASPEED_GIC_REDIST,
>       ASPEED_DEV_IPC0,
>       ASPEED_DEV_IPC1,
> +    ASPEED_DEV_LTPI_CTRL1,
> +    ASPEED_DEV_LTPI_CTRL2,
>   };
>   
>   const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index c484bcd4e2..c0d8639bde 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -86,6 +86,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
>       [ASPEED_DEV_UART10]    =  0x14C33900,
>       [ASPEED_DEV_UART11]    =  0x14C33A00,
>       [ASPEED_DEV_UART12]    =  0x14C33B00,
> +    [ASPEED_DEV_LTPI_CTRL1] =  0x14C34000,
> +    [ASPEED_DEV_LTPI_CTRL2] =  0x14C35000,
>       [ASPEED_DEV_WDT]       =  0x14C37000,
>       [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
>       [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> @@ -543,6 +545,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
>           object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
>       }
>   
> +    for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
> +        object_initialize_child(obj, "ltpi-ctrl[*]",
> +                                &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
> +    }
>       object_initialize_child(obj, "dpmcu", &s->dpmcu,
>                               TYPE_UNIMPLEMENTED_DEVICE);
>       object_initialize_child(obj, "ltpi", &s->ltpi,
> @@ -688,6 +694,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>       g_autofree char *name = NULL;
>       qemu_irq irq;
>       int uart;
> +    AspeedLTPIState *ltpi_ctrl;
> +    hwaddr ltpi_base;

These 2 variable declarations could be moved under the loop introduced
below.


Thanks,

C.


>   
>       /* Default boot region (SPI memory or ROMs) */
>       memory_region_init(&s->spi_boot_container, OBJECT(s),
> @@ -1021,6 +1029,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>           return;
>       }
>   
> +    /* LTPI controller */
> +    for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
> +        ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
> +        ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
> +
> +        if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
> +            return;
> +        }
> +        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
> +    }
>       aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
>                                     "aspeed.dpmcu",
>                                     sc->memmap[ASPEED_DEV_DPMCU],



  reply	other threads:[~2025-11-07 13:08 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-05  3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
2025-11-05  3:58 ` [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller Kane Chen via
2025-11-07 13:07   ` Cédric Le Goater
2025-11-05  3:58 ` [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
2025-11-07 13:08   ` Cédric Le Goater [this message]
2025-11-05  3:58 ` [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
2025-11-07 13:10   ` Cédric Le Goater
2025-11-05  3:58 ` [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
2025-11-07 13:30   ` Cédric Le Goater
2025-11-05  3:58 ` [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
2025-11-07 13:36   ` Cédric Le Goater
2025-11-10  2:09     ` Kane Chen
2025-11-05  3:58 ` [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
2025-11-07 13:36   ` Cédric Le Goater
2025-11-10  2:05     ` Kane Chen
2025-11-05  3:58 ` [PATCH v2 07/17] hw/arm/aspeed: Attach UART device " Kane Chen via
2025-11-10 16:04   ` Cédric Le Goater
2025-11-11  5:46     ` Jan Kiszka
2025-11-05  3:58 ` [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM " Kane Chen via
2025-11-10 16:08   ` Cédric Le Goater
2025-11-11  1:42     ` Kane Chen
2025-11-05  3:58 ` [PATCH v2 09/17] hw/arm/aspeed: Attach SPI " Kane Chen via
2025-11-05 21:20   ` Nabih Estefan
2025-11-06 10:11     ` Kane Chen
2025-11-06 10:21       ` Cédric Le Goater
2025-11-07  5:39         ` Kane Chen
2025-11-07  7:54           ` Cédric Le Goater
2025-11-05  3:58 ` [PATCH v2 10/17] hw/arm/aspeed: Attach ADC " Kane Chen via
2025-11-05  3:58 ` [PATCH v2 11/17] hw/arm/aspeed: Attach SCU " Kane Chen via
2025-11-05  3:58 ` [PATCH v2 12/17] hw/arm/aspeed: Attach GPIO " Kane Chen via
2025-11-05  3:58 ` [PATCH v2 13/17] hw/arm/aspeed: Attach I2C " Kane Chen via
2025-11-05  3:58 ` [PATCH v2 14/17] hw/arm/aspeed: Attach WDT " Kane Chen via
2025-11-05  3:58 ` [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
2025-11-07  8:06   ` Cédric Le Goater
2025-11-07  8:41     ` Kane Chen
2025-11-05  3:58 ` [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM " Kane Chen via
2025-11-10 16:14   ` Cédric Le Goater
2025-11-11  1:33     ` Kane Chen
2025-11-12  7:06       ` Cédric Le Goater
2025-11-05  3:58 ` [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM " Kane Chen via
2025-11-10 16:16   ` Cédric Le Goater
2025-11-11  1:27     ` Kane Chen
2025-11-05 10:27 ` [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Cédric Le Goater
2025-11-05 10:34   ` Kane Chen
2025-11-10 16:43 ` Cédric Le Goater
2025-11-11  2:32   ` Kane Chen

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