From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1av4uR-0003rS-Gx for qemu-devel@nongnu.org; Tue, 26 Apr 2016 11:28:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1av4uN-0007dv-7P for qemu-devel@nongnu.org; Tue, 26 Apr 2016 11:28:19 -0400 Received: from mout.web.de ([212.227.17.12]:52479) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1av4uM-0007cx-Ux for qemu-devel@nongnu.org; Tue, 26 Apr 2016 11:28:15 -0400 References: <571DA823.1030003@web.de> <20160425071806.GF3261@pxdev.xzpeter.org> <571DC61C.9020006@web.de> <20160426073426.GD28545@pxdev.xzpeter.org> <571F1F7F.5050604@web.de> <571F23B2.3000902@web.de> <20160426103819.GE28545@pxdev.xzpeter.org> <571F4840.2060800@web.de> <20160426114051.GF28545@pxdev.xzpeter.org> <571F7A14.9050805@web.de> <20160426145945.GD19789@potion> From: Jan Kiszka Message-ID: <571F8901.8000100@web.de> Date: Tue, 26 Apr 2016 17:28:01 +0200 MIME-Version: 1.0 In-Reply-To: <20160426145945.GD19789@potion> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v4 00/16] IOMMU: Enable interrupt remapping for Intel IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= Cc: Peter Xu , qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On 2016-04-26 16:59, Radim Krčmář wrote: > 2016-04-26 16:24+0200, Jan Kiszka: >> On 2016-04-26 13:40, Peter Xu wrote: >>> Currently, all the interrupts will be translated into one MSI in >>> vtd_generate_msi_message(), in which only 8 bits of dest_id is used >>> (msg.dest = irq->dest). We may possibly need to use the high 32 bits >>> of MSI address to store the rest dest[31:8]? Don't know whether this >>> would be enough though. >> >> Yes, I ran into this topic as well as I hacked up those line. Currently, >> KVM does not support more than 254 vCPUs, so 8 bits of those 32 are >> actually fine, and piggy-backing them in an MSI message works. >> >> Once KVM supports more CPUs, it has to come up with a new userspace >> interface to inject APIC events for more than 255 CPUs. Maybe the >> existing direct MSI inject with its unused flags could be "bended", >> maybe there are already better ideas (Radim?). > > Adding a flag to msi_msg and taking 3-4 bytes from padding to express > x2APIC addresses is reasonable. (It is what my prototype did. :]) > > The conceptually different idea is forcing all userspace interrupts > through irqfd routes, which would obsolete the ad-host inject. irqfd for userspace sources is a bit clumsy from the API POV. On the other hand, we need to tweak the routing API anyway to achieve the same address extension there, too. Jan > >> In any case, the KVM layer in userspace will then have to pick up all 32 >> destination bits from the IRTE and deliver them via that new interface >> to the in-kernel APICs. > > I'll keep that in mind, thanks. >