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Date: Fri, 29 Apr 2016 14:49:34 +0100
From: Leon Alrae <leon.alrae@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH v5 1/9] softfloat: Implement
 run-time-configurable meaning of signaling NaN bit
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To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, proljc@gmail.com, kbastian@mail.uni-paderborn.de, mark.cave-ayland@ilande.co.uk, agraf@suse.de, blauwirbel@gmail.com, jcmvbkbc@gmail.com, aleksandar.markovic@imgtec.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, petar.jovanovic@imgtec.com, pbonzini@redhat.com, miodrag.dinic@imgtec.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, afaerber@suse.de, aurelien@aurel32.net, rth@twiddle.net, maciej.rozycki@imgtec.com

On 18/04/16 17:03, Aleksandar Markovic wrote:
> -#if SNAN_BIT_IS_ONE
> -    return ((uint32_t)(a << 1) >= 0xff800000);
> -#else
> -    return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
> -#endif
> +    if (status->snan_bit_is_one) {
> +        return ((uint32_t)(a << 1) >= 0xFF800000);
> +    } else {
> +        return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);

Thanks for fixing the style of lines you modified, ...

> -    z.sign = float32_val(a)>>31;
> +    z.sign = float32_val(a) >> 31;
>      z.low = 0;
> -    z.high = ( (uint64_t) float32_val(a) )<<41;
> +    z.high = ((uint64_t)float32_val(a)) << 41;

... here however I think we usually don't correct the style if the line
wouldn't be touched otherwise. But obviously this is up to FPU Maintainers.

> @@ -2940,7 +2952,8 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
>          c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0);                      \
>                                                                              \
>          if (get_enabled_exceptions(env, c)) {                               \
> -            DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c;                    \
> +            DEST = ((FLOAT_SNAN ## BITS(&env->active_tc.msa_fp_status)      \

You can use the existing local pointer "status". Similarly in other MSA
macros.

> +                       >> 6) << 6) | c;                                     \


> @@ -4670,7 +4670,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>                          TCGv r_const;
>  
>                          gen_address_mask(dc, cpu_addr);
> -                        tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
> +                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);

This change appeared here by mistake, isn't it?

Thanks,
Leon