From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:54783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hJ33J-0001iD-AX for qemu-devel@nongnu.org; Tue, 23 Apr 2019 17:34:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hJ33I-000143-6O for qemu-devel@nongnu.org; Tue, 23 Apr 2019 17:34:09 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:45589) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hJ33G-0000tp-3q for qemu-devel@nongnu.org; Tue, 23 Apr 2019 17:34:08 -0400 Received: by mail-pl1-x642.google.com with SMTP id o5so3817707pls.12 for ; Tue, 23 Apr 2019 14:33:54 -0700 (PDT) References: <20190416125744.27770-1-peter.maydell@linaro.org> <20190416125744.27770-9-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <5729634a-fc95-a6bb-cb97-3daa3daeba37@linaro.org> Date: Tue, 23 Apr 2019 14:33:50 -0700 MIME-Version: 1.0 In-Reply-To: <20190416125744.27770-9-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org On 4/16/19 5:57 AM, Peter Maydell wrote: > The M-profile CONTROL register has two bits -- SFPA and FPCA -- > which relate to floating-point support, and should be RES0 otherwise. > Handle them correctly in the MSR/MRS register access code. > Neither is banked between security states, so they are stored > in v7m.control[M_REG_S] regardless of current security state. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++------- > 1 file changed, 49 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3110C10F03 for ; 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id o89sm28442078pfi.178.2019.04.23.14.33.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 14:33:52 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20190416125744.27770-1-peter.maydell@linaro.org> <20190416125744.27770-9-peter.maydell@linaro.org> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <5729634a-fc95-a6bb-cb97-3daa3daeba37@linaro.org> Date: Tue, 23 Apr 2019 14:33:50 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190416125744.27770-9-peter.maydell@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: Re: [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Message-ID: <20190423213350.aS4OUmp2BHcpNxh3gtAnl-zr3Jy_4WK4fOXPXcDXrNo@z> On 4/16/19 5:57 AM, Peter Maydell wrote: > The M-profile CONTROL register has two bits -- SFPA and FPCA -- > which relate to floating-point support, and should be RES0 otherwise. > Handle them correctly in the MSR/MRS register access code. > Neither is banked between security states, so they are stored > in v7m.control[M_REG_S] regardless of current security state. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++------- > 1 file changed, 49 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~