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From: Jan Kiszka <jan.kiszka@web.de>
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Date: Sat, 7 May 2016 15:50:37 +0200
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Subject: Re: [Qemu-devel] [PATCH 1/4] apic: add deliver_msi to
 APICCommonClass
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To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>, "Lan, Tianyu" <tianyu.lan@intel.com>, Igor Mammedov <imammedo@redhat.com>, Peter Xu <peterx@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>, Richard Henderson <rth@twiddle.net>

On 2016-05-06 22:53, Radim Krčmář wrote:
> The only way to send interrupts from outside of APIC devices is to use
> the MSI-inspired memory mapped interface.  The interface is not
> sufficient because interrupt remapping in extended mode can exceed 8 bit
> destination ids.
> 
> The proper way to deliver interrupts would be to design a bus (QPI), but
> that is a big undertaking.  Real IR unit stores excessive bits in the
> high work of MSI address register, which would be bit [63:40] in memory

s/work/word/

> address space, so I was considering two options:
>  - a new special address space for APIC to handle MSI-compatible writes
>  - one callback to the APIC class that delivers extended MSIs
> 
> This patch uses latter option, because it was easier for me, but I think
> the former one could be a tad nicer.

Makes sense.

Eventually, we should also finally untangle the MSI DMA request handling
from the xAPIC MMIO processing. The former could become pretty generic
(instead of being reimplemented by each APIC flavour), just potentially
redirected to an IOMMU when one is present. But that could come as
separate patches.

Jan