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From: Shannon Zhao <shannon.zhao@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, Pavel Fedin <p.fedin@samsung.com>,
	Shlomo Pongratz <shlomo.pongratz@huawei.com>,
	Shlomo Pongratz <shlomopongratz@gmail.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 03/23] target-arm: Define new arm_is_el3_or_mon() function
Date: Tue, 10 May 2016 21:42:38 +0800	[thread overview]
Message-ID: <5731E54E.2060006@linaro.org> (raw)
In-Reply-To: <1462814989-24360-4-git-send-email-peter.maydell@linaro.org>

On 2016年05月10日 01:29, Peter Maydell wrote:
> The GICv3 system registers need to know if the CPU is AArch64
> in EL3 or AArch32 in Monitor mode. This happens to be the first
> part of the check for arm_is_secure(), so factor it out into a
> new arm_is_el3_or_mon() function that the GIC can also use.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/cpu.h | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 066ff67..6ffc13b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -960,8 +960,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
>      }
>  }
>  
> -/* Return true if the processor is in secure state */
> -static inline bool arm_is_secure(CPUARMState *env)
> +/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
> +static bool arm_is_el3_or_mon(CPUARMState *env)
inline?

>  {
>      if (arm_feature(env, ARM_FEATURE_EL3)) {
>          if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
> @@ -973,6 +973,15 @@ static inline bool arm_is_secure(CPUARMState *env)
>              return true;
>          }
>      }
> +    return false;
> +}
> +
> +/* Return true if the processor is in secure state */
> +static inline bool arm_is_secure(CPUARMState *env)
> +{
> +    if (arm_is_el3_or_mon(env)) {
> +        return true;
> +    }
>      return arm_is_secure_below_el3(env);
>  }
>  
> 

Thanks,
-- 
Shannon

  reply	other threads:[~2016-05-10 13:42 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-09 17:29 [Qemu-devel] [PATCH 00/23] GICv3 emulation Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 01/23] migration: Define VMSTATE_UINT64_2DARRAY Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 02/23] bitops.h: Implement half-shuffle and half-unshuffle ops Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 03/23] target-arm: Define new arm_is_el3_or_mon() function Peter Maydell
2016-05-10 13:42   ` Shannon Zhao [this message]
2016-05-09 17:29 ` [Qemu-devel] [PATCH 04/23] target-arm: Provide hook to tell GICv3 about changes of security state Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 05/23] target-arm: Add mp-affinity property for ARM CPU class Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 06/23] hw/intc/arm_gicv3: Add state information Peter Maydell
2016-05-19  9:36   ` Shannon Zhao
2016-05-19  9:47     ` Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 07/23] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 08/23] hw/intc/arm_gicv3: Add vmstate descriptors Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 09/23] hw/intc/arm_gicv3: ARM GICv3 device framework Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to identify next pending irq Peter Maydell
2016-05-19 12:59   ` Shannon Zhao
2016-05-19 13:21     ` Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 11/23] hw/intc/arm_gicv3: Implement GICv3 distributor registers Peter Maydell
2016-05-13 15:05   ` Shannon Zhao
2016-05-13 15:24     ` Peter Maydell
2016-05-16  8:56       ` Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 12/23] hw/intc/arm_gicv3: Implement GICv3 redistributor registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 13/23] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 14/23] hw/intc/arm_gicv3: Implement gicv3_set_irq() Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_update() Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 17/23] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 19/23] target-arm/machine.c: Allow user to request GICv3 emulation Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 20/23] target-arm/monitor.c: Advertise emulated GICv3 in capabilities Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming interrupts are group 1 Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 22/23] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes Peter Maydell
2016-05-09 17:29 ` [Qemu-devel] [PATCH 23/23] RFC: hw/intc/arm_gicv3_kvm: Implement get/put functions Peter Maydell
2016-05-11  6:51 ` [Qemu-devel] [PATCH 00/23] GICv3 emulation Shannon Zhao
2016-05-12 13:53   ` Peter Maydell
2016-05-12 14:31     ` Shannon Zhao
2016-05-12 14:35       ` Peter Maydell
2016-05-12 15:01         ` Shannon Zhao
2016-05-12 15:22           ` Peter Maydell
2016-05-13 14:35             ` Shannon Zhao
2016-05-25 14:50 ` Shannon Zhao

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