From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46760) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2FYC-0004AG-Fo for qemu-devel@nongnu.org; Mon, 16 May 2016 06:15:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2FY8-0006qb-6V for qemu-devel@nongnu.org; Mon, 16 May 2016 06:14:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43053) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2FY7-0006qS-UM for qemu-devel@nongnu.org; Mon, 16 May 2016 06:14:56 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B56E6627D6 for ; Mon, 16 May 2016 10:14:54 +0000 (UTC) References: <1463340214-8721-1-git-send-email-marcel@redhat.com> <1463340214-8721-3-git-send-email-marcel@redhat.com> <20160516102419.43e4b016@nial.brq.redhat.com> From: Marcel Apfelbaum Message-ID: <57399D9B.50407@redhat.com> Date: Mon, 16 May 2016 13:14:51 +0300 MIME-Version: 1.0 In-Reply-To: <20160516102419.43e4b016@nial.brq.redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH V2 2/4] pci: reserve 64 bit MMIO range for PCI hotplug List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: qemu-devel@nongnu.org, mst@redhat.com, lersek@redhat.com, ehabkost@redhat.com On 05/16/2016 11:24 AM, Igor Mammedov wrote: > On Sun, 15 May 2016 22:23:32 +0300 > Marcel Apfelbaum wrote: > >> Using the firmware assigned MMIO ranges for 64-bit PCI window >> leads to zero space for hot-plugging PCI devices over 4G. >> >> PC machines can use the whole CPU addressable range after >> the space reserved for memory-hotplug. >> >> Signed-off-by: Marcel Apfelbaum >> --- >> hw/pci/pci.c | 16 ++++++++++++++-- >> 1 file changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/hw/pci/pci.c b/hw/pci/pci.c >> index bb605ef..44dd949 100644 >> --- a/hw/pci/pci.c >> +++ b/hw/pci/pci.c >> @@ -41,6 +41,7 @@ >> #include "hw/hotplug.h" >> #include "hw/boards.h" >> #include "qemu/cutils.h" >> +#include "hw/i386/pc.h" >> >> //#define DEBUG_PCI >> #ifdef DEBUG_PCI >> @@ -2467,8 +2468,19 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) >> Hi Igor, Thanks for reviewing this series. >> void pci_bus_get_w64_range(PCIBus *bus, Range *range) >> { >> - range->begin = range->end = 0; >> - pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); >> + Object *machine = qdev_get_machine(); >> + if (object_dynamic_cast(machine, TYPE_PC_MACHINE)) { >> + PCMachineState *pcms = PC_MACHINE(machine); >> + range->begin = pc_machine_get_reserved_memory_end(pcms); > that line should break linking on other targets which don't have > pc_machine_get_reserved_memory_end() > probably for got to add stub. > I cross-compiled all the targets with no problem. It seems no stub is required. >> + if (!range->begin) { >> + range->begin = ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, >> + 1ULL << 30); >> + } >> + range->end = 1ULL << 40; /* 40 bits physical */ > x86 specific in generic code > I am aware I put x86 code in the generic pci code, but I limited it with if (object_dynamic_cast(machine, TYPE_PC_MACHINE)) { So we have a generic rule for getting the w64 range and a specific one for PC machines. The alternative would be a w64 range per host-bridge, not bus. Adding a pci_bus_get_w64_range function to PCIHostBridgeClass, defaulting in current implementation for the base class and overriding it for piix/q35 looks OK to you? I thought about it, but it seemed over-engineered as opposed to the 'simple' if statement, however I can try it if you think is better. > ARM also has 64-bit PCI MMIO /git grep VIRT_PCIE_MMIO_HIGH/ I had a look and ARM does not use this infrastructure, it has its own abstractions, a memmap list. This is the other reason I selected this implementation, because is not really used by other targets (but it can be used in the future) Thanks, Marcel > perhaps range should be a property of PCI bus, > where a board sets its own values for start/size > >> + } else { >> + range->begin = range->end = 0; >> + pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); >> + } >> } >> >> static bool pcie_has_upstream_port(PCIDevice *dev) >