From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b32B9-0004yI-A6 for qemu-devel@nongnu.org; Wed, 18 May 2016 10:10:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b32B4-0007Li-5P for qemu-devel@nongnu.org; Wed, 18 May 2016 10:10:26 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:33397) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b32B3-0007LW-Sx for qemu-devel@nongnu.org; Wed, 18 May 2016 10:10:22 -0400 Received: by mail-lf0-x241.google.com with SMTP id j8so3292987lfd.0 for ; Wed, 18 May 2016 07:10:21 -0700 (PDT) References: <1463196873-17737-1-git-send-email-cota@braap.org> <1463196873-17737-8-git-send-email-cota@braap.org> <573B5134.8060104@gmail.com> <20160517193842.GB30174@flamenco> <573B80AD.50503@gmail.com> <20160517231809.GA17517@flamenco> <573C7536.7080104@gmail.com> <3c729264-24c0-e3f4-2cdd-62afb47f80e1@redhat.com> From: Sergey Fedorov Message-ID: <573C77CB.1010508@gmail.com> Date: Wed, 18 May 2016 17:10:19 +0300 MIME-Version: 1.0 In-Reply-To: <3c729264-24c0-e3f4-2cdd-62afb47f80e1@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 07/18] qemu-thread: add simple test-and-set spinlock List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , "Emilio G. Cota" Cc: QEMU Developers , MTTCG Devel , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Peter Crosthwaite , Richard Henderson On 18/05/16 17:05, Paolo Bonzini wrote: > > On 18/05/2016 15:59, Sergey Fedorov wrote: >> But actually (cf include/qemu/atomic.h) we can have: >> >> #define atomic_read(ptr) \ >> ({ \ >> QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \ >> typeof(*ptr) _val; \ >> __atomic_load(ptr, &_val, __ATOMIC_RELAXED); \ >> _val; \ >> }) >> >> >> I can't find anywhere if this __atomic_load() has volatile/compiler >> barrier semantics... > The standard says "you can have data races on atomic loads", that is > very close to compiler barrier semantics but indeed atomics.txt should > be updated to explain the C11 memory model in not-so-formal terms. > > For example this: > > atomic_set(&x, 1); > atomic_set(&y, 1); > atomic_set(&x, 2); > atomic_set(&y, 2); > > could become > > atomic_set(&x, 2); > atomic_set(&y, 2); > > with C11 atomics but not with volatile. However this: > > if (atomic_read(&x) != 1) { > atomic_set(&x, 1); > } > > couldn't become an unconditional > > atomic_set(&x, 1); Sorry, I can't figure out why it couldn't... Kind regards, Sergey