From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34216) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b32Bo-0005SB-P9 for qemu-devel@nongnu.org; Wed, 18 May 2016 10:11:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b32Bj-0007Xh-LE for qemu-devel@nongnu.org; Wed, 18 May 2016 10:11:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b32Bj-0007XV-EZ for qemu-devel@nongnu.org; Wed, 18 May 2016 10:11:03 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 237FAC05B1CD for ; Wed, 18 May 2016 14:11:03 +0000 (UTC) References: <1463340214-8721-1-git-send-email-marcel@redhat.com> <1463340214-8721-3-git-send-email-marcel@redhat.com> <20160518155929.01d7b07f@nial.brq.redhat.com> From: Marcel Apfelbaum Message-ID: <573C77F4.8080502@redhat.com> Date: Wed, 18 May 2016 17:11:00 +0300 MIME-Version: 1.0 In-Reply-To: <20160518155929.01d7b07f@nial.brq.redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH V2 2/4] pci: reserve 64 bit MMIO range for PCI hotplug List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: qemu-devel@nongnu.org, lersek@redhat.com, ehabkost@redhat.com, mst@redhat.com On 05/18/2016 04:59 PM, Igor Mammedov wrote: > On Sun, 15 May 2016 22:23:32 +0300 > Marcel Apfelbaum wrote: > >> Using the firmware assigned MMIO ranges for 64-bit PCI window >> leads to zero space for hot-plugging PCI devices over 4G. >> >> PC machines can use the whole CPU addressable range after >> the space reserved for memory-hotplug. >> >> Signed-off-by: Marcel Apfelbaum > that patch also has side effect of unconditionally adding > QWordMemory() resource in PCI0._CRS > on all machine types with QEMU generated ACPI tables. Right. > > Have you tested that it won't break boot of legacy OSes > (XP, WS2003, old linux with 32bit kernel)? I tested it with an old 32-bit CPU with a Linux guest and all I received was a warning message that is not CPU addressable and will be discarded. I didn't try it with WinXp though, I'll give it a try and report the issues, if any. Thanks, Marcel > >> --- >> hw/pci/pci.c | 16 ++++++++++++++-- >> 1 file changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/hw/pci/pci.c b/hw/pci/pci.c >> index bb605ef..44dd949 100644 >> --- a/hw/pci/pci.c >> +++ b/hw/pci/pci.c >> @@ -41,6 +41,7 @@ >> #include "hw/hotplug.h" >> #include "hw/boards.h" >> #include "qemu/cutils.h" >> +#include "hw/i386/pc.h" >> >> //#define DEBUG_PCI >> #ifdef DEBUG_PCI >> @@ -2467,8 +2468,19 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) >> >> void pci_bus_get_w64_range(PCIBus *bus, Range *range) >> { >> - range->begin = range->end = 0; >> - pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); >> + Object *machine = qdev_get_machine(); >> + if (object_dynamic_cast(machine, TYPE_PC_MACHINE)) { >> + PCMachineState *pcms = PC_MACHINE(machine); >> + range->begin = pc_machine_get_reserved_memory_end(pcms); >> + if (!range->begin) { >> + range->begin = ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, >> + 1ULL << 30); >> + } >> + range->end = 1ULL << 40; /* 40 bits physical */ >> + } else { >> + range->begin = range->end = 0; >> + pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); >> + } >> } >> >> static bool pcie_has_upstream_port(PCIDevice *dev) >