From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b32px-000865-Uw for qemu-devel@nongnu.org; Wed, 18 May 2016 10:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b32ps-0000Tl-UP for qemu-devel@nongnu.org; Wed, 18 May 2016 10:52:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41440) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b32ps-0000TY-OV for qemu-devel@nongnu.org; Wed, 18 May 2016 10:52:32 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 207FC62664 for ; Wed, 18 May 2016 14:52:32 +0000 (UTC) References: <1463340214-8721-1-git-send-email-marcel@redhat.com> <1463340214-8721-3-git-send-email-marcel@redhat.com> <20160518155929.01d7b07f@nial.brq.redhat.com> <20160518170958-mutt-send-email-mst@redhat.com> <573C7839.3090802@redhat.com> <20160518163146.7554ac6f@nial.brq.redhat.com> <20160518173737-mutt-send-email-mst@redhat.com> From: Marcel Apfelbaum Message-ID: <573C81AD.7080603@redhat.com> Date: Wed, 18 May 2016 17:52:29 +0300 MIME-Version: 1.0 In-Reply-To: <20160518173737-mutt-send-email-mst@redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH V2 2/4] pci: reserve 64 bit MMIO range for PCI hotplug List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" , Igor Mammedov Cc: qemu-devel@nongnu.org, lersek@redhat.com, ehabkost@redhat.com On 05/18/2016 05:42 PM, Michael S. Tsirkin wrote: > On Wed, May 18, 2016 at 04:31:46PM +0200, Igor Mammedov wrote: >> On Wed, 18 May 2016 17:12:09 +0300 >> Marcel Apfelbaum wrote: >> >>> On 05/18/2016 05:11 PM, Michael S. Tsirkin wrote: >>>> On Wed, May 18, 2016 at 03:59:29PM +0200, Igor Mammedov wrote: >>>>> On Sun, 15 May 2016 22:23:32 +0300 >>>>> Marcel Apfelbaum wrote: >>>>> >>>>>> Using the firmware assigned MMIO ranges for 64-bit PCI window >>>>>> leads to zero space for hot-plugging PCI devices over 4G. >>>>>> >>>>>> PC machines can use the whole CPU addressable range after >>>>>> the space reserved for memory-hotplug. >>>>>> >>>>>> Signed-off-by: Marcel Apfelbaum >>>>> that patch also has side effect of unconditionally adding >>>>> QWordMemory() resource in PCI0._CRS >>>>> on all machine types with QEMU generated ACPI tables. >>>>> >>>>> Have you tested that it won't break boot of legacy OSes >>>>> (XP, WS2003, old linux with 32bit kernel)? >>>> >>>> It's almost sure it break it. >>>> Maybe you can check _REV in _CRS to work around this for XP. >>> >>> I'll try it. >> but only after you check if just presence of QWord would crash XP, >> so in case it doesn't crash we would keep _CRS simple static >> structure. >> >> I very vaguely recall that XP ignored QWord in PCI0._CRS, >> but it was long time ago so it won't hurt to recheck. > > I played with different guests (32 and 64 bit) > at some point. > > Generally, windows tends to crash when CRS resources exceed the > supported limits > of physical memory (sometimes with weird off by one errors, > e.g. win7 32 bit seems to survive with a 36 bit pci hole even though > this means the max address is 2^37-1 which it can't address). > > This might depend on CPU as well. It seems QEMU returns 40-bit as CPU addressable bits, but I might got it wrong. > > Which makes me ask: why don't we fix this in BIOS? > If you want it to allocate a large window, do it. I don't follow, BIOS can assign resources to PCI devices, but how to specify a MMIO range for hot-plug? Add it to the CRS of the host-bridge, right? Thanks, Marcel [...]