From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37701) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3F1P-00085u-HA for qemu-devel@nongnu.org; Wed, 18 May 2016 23:53:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b3F1M-0002vH-Ay for qemu-devel@nongnu.org; Wed, 18 May 2016 23:53:15 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50354) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3F1M-0002us-1s for qemu-devel@nongnu.org; Wed, 18 May 2016 23:53:12 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 934E76331B for ; Thu, 19 May 2016 03:53:11 +0000 (UTC) References: <1463589381-66853-1-git-send-email-pbonzini@redhat.com> <1463589381-66853-6-git-send-email-pbonzini@redhat.com> From: Thomas Huth Message-ID: <573D38A4.60200@redhat.com> Date: Thu, 19 May 2016 05:53:08 +0200 MIME-Version: 1.0 In-Reply-To: <1463589381-66853-6-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 16/52] target-ppc: make cpu-qom.h not target specific List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org On 18.05.2016 18:36, Paolo Bonzini wrote: > Make PowerPCCPU an opaque type within cpu-qom.h, and move all definitions > of private methods, as well as all type definitions that require knowledge > of the layout to cpu.h. Conversely, move all definitions needed to define > a class to cpu-qom.h. This helps making files independent of NEED_CPU_H > if they only need to pass around CPU pointers. > > Signed-off-by: Paolo Bonzini > --- > target-ppc/cpu-qom.h | 161 ++++++++++++++++++++++++++++++++++---------------- > target-ppc/cpu.h | 164 ++++++++++++++++----------------------------------- > 2 files changed, 163 insertions(+), 162 deletions(-) > > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h > index 6f4e929..9429bc9 100644 > --- a/target-ppc/cpu-qom.h > +++ b/target-ppc/cpu-qom.h > @@ -38,6 +38,117 @@ > OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) > > typedef struct PowerPCCPU PowerPCCPU; > +typedef struct CPUPPCState CPUPPCState; > +typedef struct ppc_tb_t ppc_tb_t; > +typedef struct ppc_dcr_t ppc_dcr_t; > + > +/*****************************************************************************/ > +/* MMU model */ > +typedef enum powerpc_mmu_t powerpc_mmu_t; > +enum powerpc_mmu_t { > + POWERPC_MMU_UNKNOWN = 0x00000000, > + /* Standard 32 bits PowerPC MMU */ > + POWERPC_MMU_32B = 0x00000001, > + /* PowerPC 6xx MMU with software TLB */ > + POWERPC_MMU_SOFT_6xx = 0x00000002, > + /* PowerPC 74xx MMU with software TLB */ > + POWERPC_MMU_SOFT_74xx = 0x00000003, > + /* PowerPC 4xx MMU with software TLB */ > + POWERPC_MMU_SOFT_4xx = 0x00000004, > + /* PowerPC 4xx MMU with software TLB and zones protections */ > + POWERPC_MMU_SOFT_4xx_Z = 0x00000005, > + /* PowerPC MMU in real mode only */ > + POWERPC_MMU_REAL = 0x00000006, > + /* Freescale MPC8xx MMU model */ > + POWERPC_MMU_MPC8xx = 0x00000007, > + /* BookE MMU model */ > + POWERPC_MMU_BOOKE = 0x00000008, > + /* BookE 2.06 MMU model */ > + POWERPC_MMU_BOOKE206 = 0x00000009, > + /* PowerPC 601 MMU model (specific BATs format) */ > + POWERPC_MMU_601 = 0x0000000A, > +#if defined(TARGET_PPC64) > +#define POWERPC_MMU_64 0x00010000 > +#define POWERPC_MMU_1TSEG 0x00020000 > +#define POWERPC_MMU_AMR 0x00040000 > + /* 64 bits PowerPC MMU */ > + POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, > + /* Architecture 2.03 and later (has LPCR) */ > + POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, > + /* Architecture 2.06 variant */ > + POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > + | POWERPC_MMU_AMR | 0x00000003, > + /* Architecture 2.06 "degraded" (no 1T segments) */ > + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR > + | 0x00000003, > + /* Architecture 2.07 variant */ > + POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > + | POWERPC_MMU_AMR | 0x00000004, > + /* Architecture 2.07 "degraded" (no 1T segments) */ > + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR > + | 0x00000004, > +#endif /* defined(TARGET_PPC64) */ > +}; > + > +/*****************************************************************************/ > +/* Exception model */ > +typedef enum powerpc_excp_t powerpc_excp_t; > +enum powerpc_excp_t { > + POWERPC_EXCP_UNKNOWN = 0, > + /* Standard PowerPC exception model */ > + POWERPC_EXCP_STD, > + /* PowerPC 40x exception model */ > + POWERPC_EXCP_40x, > + /* PowerPC 601 exception model */ > + POWERPC_EXCP_601, > + /* PowerPC 602 exception model */ > + POWERPC_EXCP_602, > + /* PowerPC 603 exception model */ > + POWERPC_EXCP_603, > + /* PowerPC 603e exception model */ > + POWERPC_EXCP_603E, > + /* PowerPC G2 exception model */ > + POWERPC_EXCP_G2, > + /* PowerPC 604 exception model */ > + POWERPC_EXCP_604, > + /* PowerPC 7x0 exception model */ > + POWERPC_EXCP_7x0, > + /* PowerPC 7x5 exception model */ > + POWERPC_EXCP_7x5, > + /* PowerPC 74xx exception model */ > + POWERPC_EXCP_74xx, > + /* BookE exception model */ > + POWERPC_EXCP_BOOKE, > + /* PowerPC 970 exception model */ > + POWERPC_EXCP_970, > + /* POWER7 exception model */ > + POWERPC_EXCP_POWER7, > + /* POWER8 exception model */ > + POWERPC_EXCP_POWER8, > +}; Hmm, now you've removed the "#if defined(TARGET_PPC64)" from the enum powerpc_excp_t, but you kept it in the enum powerpc_mmu_t ... in case you respin, maybe remove it from powerpc_mmu_t, too? Thomas