From: Jan Kiszka <jan.kiszka@web.de>
To: marcel@redhat.com, David Kiarie <davidkiarie4@gmail.com>,
Peter Xu <peterx@redhat.com>
Cc: ehabkost@redhat.com, "Michael S. Tsirkin" <mst@redhat.com>,
jasowang@redhat.com, rkrcmar@redhat.com,
QEMU Developers <qemu-devel@nongnu.org>,
alex.williamson@redhat.com, wexu@redhat.com, pbonzini@redhat.com,
imammedo@redhat.com, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class
Date: Tue, 24 May 2016 12:40:14 +0200 [thread overview]
Message-ID: <57442F8E.1090302@web.de> (raw)
In-Reply-To: <57437AAF.4060905@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1564 bytes --]
On 2016-05-23 23:48, Marcel Apfelbaum wrote:
> On 05/23/2016 08:06 PM, David Kiarie wrote:
>> On Tue, May 17, 2016 at 10:15 AM, Peter Xu <peterx@redhat.com> wrote:
>>> Introducing parent class for intel-iommu devices named "x86-iommu". This
>>> is preparation work to abstract shared functionalities out from Intel
>>> and AMD IOMMUs. Currently, only the parent class is introduced. It does
>>> nothing yet.
>>>
>>> Signed-off-by: Peter Xu <peterx@redhat.com>
>>> ---
>>> hw/i386/Makefile.objs | 2 +-
>
> [...]
>
>>> +
>>> +static const TypeInfo x86_iommu_info = {
>>> + .name = TYPE_X86_IOMMU_DEVICE,
>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>> + .instance_size = sizeof(X86IOMMUState),
>>> + .class_init = x86_iommu_class_init,
>>> + .class_size = sizeof(X86IOMMUClass),
>>> + .abstract = true,
>>> +};
>>
>> As I suspected am having some trouble parenting a PCI device from a
>> Bus device but I will investigate further to see if I can manage
>> something.
>>
>
> You cannot derive from both SYS_BUS_DEVICE and PCI_DEVICE.
> You would need a composition; your device would be a SYS_BUS_DEVICE
> and its state would include a PCI_DEVICE (or the other way around).
> Then you can divide the responsibilities between them.
Given that the AMD IOMMU is more a platform than a PCI device, I would
also go for deriving from SYS_BUS_DEVICE (and later on a common x86
IOMMU class) and embedding a PCI_DEVICE. And the Intel IOMMU has no PCI
device feature at all.
Jan
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next prev parent reply other threads:[~2016-05-24 10:40 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-17 7:15 [Qemu-devel] [PATCH v7 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 01/25] acpi: enable INTR for DMAR report structure Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 02/25] intel_iommu: allow queued invalidation for IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 03/25] intel_iommu: set IR bit for ECAP register Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 04/25] acpi: add DMAR scope definition for root IOAPIC Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 05/25] intel_iommu: define interrupt remap table addr register Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 06/25] intel_iommu: handle interrupt remap enable Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR Peter Xu
2016-05-29 8:20 ` David Kiarie
2016-05-29 8:21 ` David Kiarie
2016-05-30 5:45 ` Peter Xu
2016-05-30 5:56 ` Jan Kiszka
2016-05-30 8:14 ` Peter Xu
2016-05-30 8:54 ` David Kiarie
2016-05-30 9:16 ` Peter Xu
2016-05-30 9:25 ` David Kiarie
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class Peter Xu
2016-05-23 17:06 ` David Kiarie
2016-05-23 21:48 ` Marcel Apfelbaum
2016-05-24 10:40 ` Jan Kiszka [this message]
2016-05-24 11:02 ` David Kiarie
2016-05-24 11:29 ` David Kiarie
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 09/25] x86-iommu: provide x86_iommu_get_default Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 10/25] x86-iommu: q35: generalize find_add_as() Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 11/25] intel_iommu: add IR translation faults defines Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 12/25] intel_iommu: Add support for PCI MSI remap Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 13/25] q35: ioapic: add support for emulated IOAPIC IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 14/25] ioapic: introduce ioapic_entry_parse() helper Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 15/25] intel_iommu: add support for split irqchip Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 16/25] q35: add "intremap" parameter to enable IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 17/25] x86-iommu: introduce IEC notifiers Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 18/25] ioapic: register IOMMU IEC notifier for ioapic Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 19/25] intel_iommu: Add support for Extended Interrupt Mode Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 20/25] intel_iommu: add SID validation for IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 21/25] kvm-irqchip: simplify kvm_irqchip_add_msi_route Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 22/25] kvm-irqchip: i386: add hook for add/remove virq Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 23/25] kvm-irqchip: x86: add msi route notify fn Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 24/25] kvm-irqchip: do explicit commit when update irq Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 25/25] intel_iommu: support all masks in interrupt entry cache invalidation Peter Xu
2016-05-17 7:22 ` [Qemu-devel] [PATCH v7 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
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