From: Thomas Huth <thuth@redhat.com>
To: "David Gibson" <david@gibson.dropbear.id.au>,
"Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode
Date: Fri, 27 May 2016 06:41:52 +0200 [thread overview]
Message-ID: <5747D010.2060409@redhat.com> (raw)
In-Reply-To: <20160527033832.GS17226@voom.fritz.box>
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On 27.05.2016 05:38, David Gibson wrote:
> On Tue, May 03, 2016 at 06:03:29PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> We use an env. flag which is set to the initial value of MSR_HVB in
>> the msr_mask. We also adjust the POWER8 mask to set SHV.
>>
>> Also use this to adjust ctx.hv so that it is *set* when the processor
>> doesn't have an HV mode (970 with Apple mode for example), thus enabling
>> hypervisor instructions/SPRs.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> target-ppc/cpu.h | 4 ++++
>> target-ppc/translate.c | 4 +++-
>> target-ppc/translate_init.c | 21 ++++++++++++++++-----
>> 3 files changed, 23 insertions(+), 6 deletions(-)
...
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 10a92fdbbdd7..df656e6021b4 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8579,7 +8579,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
>> PPC2_TM;
>> pcc->msr_mask = (1ull << MSR_SF) |
>> - (1ull << MSR_TM) |
>> + (1ull << MSR_SHV) |
>> + (1ull << MSR_TM) |
>> (1ull << MSR_VR) |
>> (1ull << MSR_VSX) |
>> (1ull << MSR_EE) |
This indentation looks somewhat suspicious ... and indeed, checkpatch
compains here:
ERROR: code indent should never use tabs
#153: FILE: target-ppc/translate_init.c:8583:
+^I^I (1ull << MSR_TM) |$
total: 1 errors, 0 warnings, 60 lines checked
Please fix it to use spaces instead.
Thomas
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next prev parent reply other threads:[~2016-05-27 4:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-03 16:03 [Qemu-devel] [PATCH 00/12] ppc: preparing pnv landing (round 2) Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 01/12] ppc: Remove MMU_MODEn_SUFFIX definitions Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 02/12] ppc: Use split I/D mmu modes to avoid flushes on interrupts Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 03/12] ppc: Do some batching of TCG tlb flushes Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 04/12] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 05/12] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 06/12] ppc: Fix rfi/rfid/hrfi/... emulation Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 07/12] ppc: Better figure out if processor has HV mode Cédric Le Goater
2016-05-27 3:38 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2016-05-27 4:41 ` Thomas Huth [this message]
2016-05-27 8:10 ` Cédric Le Goater
2016-05-27 7:56 ` Cédric Le Goater
2016-05-28 9:52 ` David Gibson
2016-05-28 11:04 ` Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 08/12] ppc: tlbie, tlbia and tlbisync are HV only Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 09/12] ppc: Change 'invalid' bit mask of tlbiel and tlbie Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 10/12] ppc: Fix sign extension issue in mtmsr(d) emulation Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 11/12] ppc: Get out of emulation on SMT "OR" ops Cédric Le Goater
2016-05-03 16:03 ` [Qemu-devel] [PATCH 12/12] ppc: Add PPC_64H instruction flag to POWER7 and POWER8 Cédric Le Goater
2016-05-03 16:52 ` [Qemu-devel] [PATCH 00/12] ppc: preparing pnv landing (round 2) David Gibson
2016-05-27 3:54 ` [Qemu-devel] [Qemu-ppc] " David Gibson
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