From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6Cdf-0002qx-Ct for qemu-devel@nongnu.org; Fri, 27 May 2016 03:57:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b6CdZ-000611-BR for qemu-devel@nongnu.org; Fri, 27 May 2016 03:56:58 -0400 Received: from 5.mo179.mail-out.ovh.net ([46.105.43.140]:38199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6CdZ-00060l-2f for qemu-devel@nongnu.org; Fri, 27 May 2016 03:56:53 -0400 Received: from player715.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id BE5CDFF9337 for ; Fri, 27 May 2016 09:56:47 +0200 (CEST) References: <1462291414-8343-1-git-send-email-clg@kaod.org> <1462291414-8343-8-git-send-email-clg@kaod.org> <20160527033832.GS17226@voom.fritz.box> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <5747FDB0.4030602@kaod.org> Date: Fri, 27 May 2016 09:56:32 +0200 MIME-Version: 1.0 In-Reply-To: <20160527033832.GS17226@voom.fritz.box> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 05/27/2016 05:38 AM, David Gibson wrote: > On Tue, May 03, 2016 at 06:03:29PM +0200, C=E9dric Le Goater wrote: >> From: Benjamin Herrenschmidt >> >> We use an env. flag which is set to the initial value of MSR_HVB in >> the msr_mask. We also adjust the POWER8 mask to set SHV. >> >> Also use this to adjust ctx.hv so that it is *set* when the processor >> doesn't have an HV mode (970 with Apple mode for example), thus enabli= ng >> hypervisor instructions/SPRs. >> >> Signed-off-by: Benjamin Herrenschmidt >> Reviewed-by: David Gibson >> --- >> target-ppc/cpu.h | 4 ++++ >> target-ppc/translate.c | 4 +++- >> target-ppc/translate_init.c | 21 ++++++++++++++++----- >> 3 files changed, 23 insertions(+), 6 deletions(-) >> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h >> index 2a96efcbf813..02f2e72e6d14 100644 >> --- a/target-ppc/cpu.h >> +++ b/target-ppc/cpu.h >> @@ -1161,6 +1161,10 @@ struct CPUPPCState { >> hwaddr mpic_iack; >> /* true when the external proxy facility mode is enabled */ >> bool mpic_proxy; >> + /* set when the processor has an HV mode, thus HV priv >> + * instructions and SPRs are diallowed if MSR:HV is 0 >> + */ >> + bool has_hv_mode; >> #endif >> =20 >> /* Those resources are used only during code translation */ >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 7a672cba796d..6f55bcd34a74 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -11495,8 +11495,10 @@ void gen_intermediate_code(CPUPPCState *env, = struct TranslationBlock *tb) >> ctx.exception =3D POWERPC_EXCP_NONE; >> ctx.spr_cb =3D env->spr_cb; >> ctx.pr =3D msr_pr; >> - ctx.hv =3D !msr_pr && msr_hv; >=20 > The test for msr_pr has been removed in the new version. Maybe that's > safe, but I think it needs some justification. I don't know if it is safe to run with (MSR_HV|MSR_PR) =3D 11 =20 There is a note in the Power ISA book describing such a case but I am not= =20 sure qemu-ppc supports that. So I will keep the msr_pr check in the next=20 version : ctx.hv =3D !msr_pr && (msr_hv || !env->has_hv_mode); =20 Thanks, C. >> ctx.mem_idx =3D env->dmmu_idx; >> +#if !defined(CONFIG_USER_ONLY) >> + ctx.hv =3D msr_hv || !env->has_hv_mode; >> +#endif >> ctx.insns_flags =3D env->insns_flags; >> ctx.insns_flags2 =3D env->insns_flags2; >> ctx.access_type =3D -1; >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >> index 10a92fdbbdd7..df656e6021b4 100644 >> --- a/target-ppc/translate_init.c >> +++ b/target-ppc/translate_init.c >> @@ -8579,7 +8579,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *da= ta) >> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 = | >> PPC2_TM; >> pcc->msr_mask =3D (1ull << MSR_SF) | >> - (1ull << MSR_TM) | >> + (1ull << MSR_SHV) | >> + (1ull << MSR_TM) | >> (1ull << MSR_VR) | >> (1ull << MSR_VSX) | >> (1ull << MSR_EE) | >> @@ -9975,10 +9976,7 @@ static void ppc_cpu_reset(CPUState *s) >> pcc->parent_reset(s); >> =20 >> msr =3D (target_ulong)0; >> - if (0) { >> - /* XXX: find a suitable condition to enable the hypervisor mo= de */ >> - msr |=3D (target_ulong)MSR_HVB; >> - } >> + msr |=3D (target_ulong)MSR_HVB; >> msr |=3D (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ >> msr |=3D (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ >> msr |=3D (target_ulong)1 << MSR_EP; >> @@ -10079,6 +10077,19 @@ static void ppc_cpu_initfn(Object *obj) >> env->bfd_mach =3D pcc->bfd_mach; >> env->check_pow =3D pcc->check_pow; >> =20 >> + /* Mark HV mode as supported if the CPU has an MSR_HV bit >> + * in the msr_mask. The mask can later be cleared by PAPR >> + * mode but the hv mode support will remain, thus enforcing >> + * that we cannot use priv. instructions in guest in PAPR >> + * mode. For 970 we currently simply don't set HV in msr_mask >> + * thus simulating an "Apple mode" 970. If we ever want to >> + * support 970 HV mode, we'll have to add a processor attribute >> + * of some sort. >> + */ >> +#if !defined(CONFIG_USER_ONLY) >> + env->has_hv_mode =3D !!(env->msr_mask & MSR_HVB); >> +#endif >> + >> #if defined(TARGET_PPC64) >> if (pcc->sps) { >> env->sps =3D *pcc->sps; >=20