From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6EhG-0004Ms-Pu for qemu-devel@nongnu.org; Fri, 27 May 2016 06:08:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b6EhD-0007js-Dt for qemu-devel@nongnu.org; Fri, 27 May 2016 06:08:50 -0400 Received: from mail-lb0-x22a.google.com ([2a00:1450:4010:c04::22a]:33590) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6EhD-0007jl-28 for qemu-devel@nongnu.org; Fri, 27 May 2016 06:08:47 -0400 Received: by mail-lb0-x22a.google.com with SMTP id k7so30774779lbm.0 for ; Fri, 27 May 2016 03:08:46 -0700 (PDT) References: <1464310815-13554-1-git-send-email-rth@twiddle.net> <1464310815-13554-2-git-send-email-rth@twiddle.net> From: Sergey Fedorov Message-ID: <57481CAC.4070205@gmail.com> Date: Fri, 27 May 2016 13:08:44 +0300 MIME-Version: 1.0 In-Reply-To: <1464310815-13554-2-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 01/12] Introduce TCGOpcode for fence instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: bobby.prani@gmail.com On 27/05/16 04:00, Richard Henderson wrote: > diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h > index 6d0410c..b772d90 100644 > --- a/tcg/tcg-opc.h > +++ b/tcg/tcg-opc.h > @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) > # define IMPL64 TCG_OPF_64BIT > #endif > > +DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS) > + I still think this TCG op needs to have a constant argument of a barrier type. So that we can distinguish between full, read and write memory barriers. Regards, Sergey > DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) > DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) > DEF(setcond_i32, 1, 2, 1, 0)