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From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, Shlomo Pongratz <shlomo.pongratz@huawei.com>,
	Shlomo Pongratz <shlomopongratz@gmail.com>,
	Pavel Fedin <p.fedin@samsung.com>,
	Shannon Zhao <shannon.zhao@linaro.org>,
	Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v2 03/22] target-arm: Define new arm_is_el3_or_mon() function
Date: Tue, 7 Jun 2016 14:32:16 +0800	[thread overview]
Message-ID: <57566A70.80304@huawei.com> (raw)
In-Reply-To: <1464274540-19693-4-git-send-email-peter.maydell@linaro.org>



On 2016/5/26 22:55, Peter Maydell wrote:
> The GICv3 system registers need to know if the CPU is AArch64
> in EL3 or AArch32 in Monitor mode. This happens to be the first
> part of the check for arm_is_secure(), so factor it out into a
> new arm_is_el3_or_mon() function that the GIC can also use.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

> ---
>  target-arm/cpu.h | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index c741b53..2fa1f41 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1133,8 +1133,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
>      }
>  }
>  
> -/* Return true if the processor is in secure state */
> -static inline bool arm_is_secure(CPUARMState *env)
> +/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
> +static inline bool arm_is_el3_or_mon(CPUARMState *env)
>  {
>      if (arm_feature(env, ARM_FEATURE_EL3)) {
>          if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
> @@ -1146,6 +1146,15 @@ static inline bool arm_is_secure(CPUARMState *env)
>              return true;
>          }
>      }
> +    return false;
> +}
> +
> +/* Return true if the processor is in secure state */
> +static inline bool arm_is_secure(CPUARMState *env)
> +{
> +    if (arm_is_el3_or_mon(env)) {
> +        return true;
> +    }
>      return arm_is_secure_below_el3(env);
>  }
>  
> 

-- 
Shannon

  reply	other threads:[~2016-06-07  6:36 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-26 14:55 [Qemu-devel] [PATCH v2 00/22] GICv3 emulation Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 01/22] migration: Define VMSTATE_UINT64_2DARRAY Peter Maydell
2016-06-07  3:32   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 02/22] bitops.h: Implement half-shuffle and half-unshuffle ops Peter Maydell
2016-06-07  6:35   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 03/22] target-arm: Define new arm_is_el3_or_mon() function Peter Maydell
2016-06-07  6:32   ` Shannon Zhao [this message]
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 04/22] target-arm: Provide hook to tell GICv3 about changes of security state Peter Maydell
2016-06-14  1:49   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 05/22] target-arm: Add mp-affinity property for ARM CPU class Peter Maydell
2016-06-07  7:55   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 06/22] hw/intc/arm_gicv3: Add state information Peter Maydell
2016-06-07  7:51   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 07/22] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure Peter Maydell
2016-06-07  8:33   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 08/22] hw/intc/arm_gicv3: Add vmstate descriptors Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 09/22] hw/intc/arm_gicv3: ARM GICv3 device framework Peter Maydell
2016-06-07  9:01   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 10/22] hw/intc/arm_gicv3: Implement functions to identify next pending irq Peter Maydell
2016-06-08  1:57   ` Shannon Zhao
2016-06-09 15:24     ` Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 11/22] hw/intc/arm_gicv3: Implement GICv3 distributor registers Peter Maydell
2016-06-13  6:27   ` Shannon Zhao
2016-06-13  9:04     ` Peter Maydell
2016-06-13  9:35       ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 12/22] hw/intc/arm_gicv3: Implement GICv3 redistributor registers Peter Maydell
2016-06-14  3:09   ` Shannon Zhao
2016-06-14 12:25     ` Peter Maydell
2016-06-14 12:28       ` Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 13/22] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions Peter Maydell
2016-06-13  7:19   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq() Peter Maydell
2016-06-13  7:49   ` Shannon Zhao
2016-06-13  9:07     ` Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 15/22] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 16/22] hw/intc/arm_gicv3: Implement gicv3_cpuif_update() Peter Maydell
2016-06-13  7:56   ` Shannon Zhao
2016-06-13  9:10     ` Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 17/22] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers Peter Maydell
2016-06-14  6:24   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 18/22] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 19/22] target-arm/machine.c: Allow user to request GICv3 emulation Peter Maydell
2016-06-13 11:38   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 20/22] target-arm/monitor.c: Advertise emulated GICv3 in capabilities Peter Maydell
2016-06-13 11:40   ` Shannon Zhao
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 21/22] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes Peter Maydell
2016-06-13 11:51   ` Shannon Zhao
2016-06-13 12:02     ` Peter Maydell
2016-05-26 14:55 ` [Qemu-devel] [PATCH v2 22/22] RFC: hw/intc/arm_gicv3_kvm: Implement get/put functions Peter Maydell
2016-05-30 11:15 ` [Qemu-devel] [PATCH v2 00/22] GICv3 emulation Andrew Jones
2016-06-06 14:42 ` [Qemu-devel] [Qemu-arm] " Peter Maydell

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