From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAAd3-0002vJ-IK for qemu-devel@nongnu.org; Tue, 07 Jun 2016 02:36:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bAAcx-0004e1-NN for qemu-devel@nongnu.org; Tue, 07 Jun 2016 02:36:44 -0400 Message-ID: <57566A70.80304@huawei.com> Date: Tue, 7 Jun 2016 14:32:16 +0800 From: Shannon Zhao MIME-Version: 1.0 References: <1464274540-19693-1-git-send-email-peter.maydell@linaro.org> <1464274540-19693-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1464274540-19693-4-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 03/22] target-arm: Define new arm_is_el3_or_mon() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Shlomo Pongratz , Shlomo Pongratz , Pavel Fedin , Shannon Zhao , Christoffer Dall On 2016/5/26 22:55, Peter Maydell wrote: > The GICv3 system registers need to know if the CPU is AArch64 > in EL3 or AArch32 in Monitor mode. This happens to be the first > part of the check for arm_is_secure(), so factor it out into a > new arm_is_el3_or_mon() function that the GIC can also use. > > Signed-off-by: Peter Maydell Reviewed-by: Shannon Zhao > --- > target-arm/cpu.h | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index c741b53..2fa1f41 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1133,8 +1133,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) > } > } > > -/* Return true if the processor is in secure state */ > -static inline bool arm_is_secure(CPUARMState *env) > +/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ > +static inline bool arm_is_el3_or_mon(CPUARMState *env) > { > if (arm_feature(env, ARM_FEATURE_EL3)) { > if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { > @@ -1146,6 +1146,15 @@ static inline bool arm_is_secure(CPUARMState *env) > return true; > } > } > + return false; > +} > + > +/* Return true if the processor is in secure state */ > +static inline bool arm_is_secure(CPUARMState *env) > +{ > + if (arm_is_el3_or_mon(env)) { > + return true; > + } > return arm_is_secure_below_el3(env); > } > > -- Shannon