From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQb71-0003WF-I1 for qemu-devel@nongnu.org; Fri, 22 Jul 2016 10:07:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bQb6w-0007sr-JP for qemu-devel@nongnu.org; Fri, 22 Jul 2016 10:07:34 -0400 References: <1469192408-21713-1-git-send-email-michael@walle.cc> <3B05311A-964D-4702-9C18-CFF265065388@suse.de> <78e83644673b8869a3d183e74ac256dc@walle.cc> From: Alexander Graf Message-ID: <579228A0.6050302@suse.de> Date: Fri, 22 Jul 2016 16:07:28 +0200 MIME-Version: 1.0 In-Reply-To: <78e83644673b8869a3d183e74ac256dc@walle.cc> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-ppc: set MSR_CM bit for BookE 2.06 MMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Walle Cc: David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 07/22/2016 03:46 PM, Michael Walle wrote: > Am 2016-07-22 15:07, schrieb Alexander Graf: >>> On 22 Jul 2016, at 15:00, Michael Walle wrote: >>> >>> 64 bit user mode doesn't work for the e5500 core because the MSR_CM=20 >>> bit is >>> not set which enables the 64 bit mode for this MMU model. Memory=20 >>> addresses >>> are truncated to 32 bit, which results in "Invalid data memory access= " >>> error messages. Fix it by setting the MSR_CM bit for this MMU model. >>> >>> Signed-off-by: Michael Walle >>> --- >>> target-ppc/translate_init.c | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.= c >>> index 5ecafc7..1ebb143 100644 >>> --- a/target-ppc/translate_init.c >>> +++ b/target-ppc/translate_init.c >>> @@ -10218,6 +10218,9 @@ static void ppc_cpu_reset(CPUState *s) >>> if (env->mmu_model & POWERPC_MMU_64) { >>> msr |=3D (1ULL << MSR_SF); >>> } >>> + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { >> >> Is this check correct? Doesn=E2=80=99t e500mc adhere to 2.06 as well? = Running >> >> qemu-system-ppc64 -M ppce500 -cpu e500mc =E2=80=A6 >> >> is perfectly valid and should just work. With your patch, it would >> start in invalid 64bit mode :). >> >> >> Alex > > Mhh, sorry I don't really have any understanding of the PPC state=20 > after reset. Should have flagged this as RFC. > > Maybe I should explain my issue. I'm debugging a problem with the 64=20 > bit linux-user variant (qemu-ppc64). There the first instructions=20 > causes an "Invalid data memory access" because the address is=20 > truncated to 32 bit. This is because the msr_is_64bit() returns false=20 > in my case. So first question here, is qemu-ppc64 supposed to set the=20 > MSR to 64bit mode? I guess so, because 32bit mode would be the=20 > qemu-ppc binary. What is the MSR state in full system emulation for a=20 > e5500 core? 64bit or 32bit? It depends on the target. Usually the reset vector is used for system=20 emulation. But apparently you're targeting user mode emulation, so the=20 reset MSR really goes to linux-user/main.c. We already set MSR_SF there=20 for 64bit binaries, I guess you'd have to check on the cpu flavor and=20 just set either SF or CM depending on cpu flags (PPC2_BOOKE206 maybe?)=20 in there. Alex > > If it is 32bit, the simple solution would be to put #ifdef=20 > CONFIG_USER_ONLY around my patch, right? > If the MMU is in 64bit mode after reset, I would have to check for the=20 > e5500, too. Mhh, I don't see that this information is available in=20 > ppc_cpu_reset(). > > -michael >