From: Richard Henderson <richard.henderson@linaro.org>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, qemu-devel@nongnu.org
Cc: Greg Favor <gfavor@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext
Date: Mon, 31 Jan 2022 07:54:28 +1100 [thread overview]
Message-ID: <57a6aec2-de05-dd33-1428-0c2c998d86ef@linaro.org> (raw)
In-Reply-To: <20220128145642.1305416-5-philipp.tomsich@vrull.eu>
On 1/29/22 01:56, Philipp Tomsich wrote:
> The Zb[abcs] support code still uses the RISCV_CPU macros to access
> the configuration information (i.e., check whether an extension is
> available/enabled). Now that we provide this information directly
> from DisasContext, we can access this directly via the cfg_ptr field.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
>
> ---
>
> Changes in v3:
> - (new patch) change Zb[abcs] implementation to use cfg_ptr (copied
> into DisasContext) instead of going throuhg RISCV_CPU
>
> target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-01-30 20:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
2022-01-30 20:52 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
2022-01-30 20:53 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
2022-01-30 20:54 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext Philipp Tomsich
2022-01-30 20:54 ` Richard Henderson [this message]
2022-01-28 14:56 ` [PATCH v3 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
2022-01-30 20:56 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
2022-01-30 21:06 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Philipp Tomsich
2022-01-30 21:06 ` Richard Henderson
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