From: Richard Henderson <richard.henderson@linaro.org>
To: Mayuresh Chitale <mchitale@ventanamicro.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com
Cc: Alistair Francis <alistair23@gmail.com>,
Daniel Barboza <dbarboza@ventanamicro.com>,
liweiwei@iscas.ac.cn
Subject: Re: [RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags
Date: Mon, 10 Apr 2023 18:47:11 -0700 [thread overview]
Message-ID: <58021b23-dc58-bf3f-b83e-ddaa5be90e14@linaro.org> (raw)
In-Reply-To: <20230410141316.3317474-3-mchitale@ventanamicro.com>
On 4/10/23 07:13, Mayuresh Chitale wrote:
> The state of smstateen0.FCSR bit impacts the execution of floating point
> instructions when misa.F==0. Add a field in the tb->flags which stores
> the current state of smstateen0.fcsr and will be used by floating point
> translation routines.
Are you certain that you require a new bit?
Could the same effect be achieved by forcing one or more of the existing
TB_FLAGS.{FS,HS_FS} fields to 0 within cpu_get_tb_cpu_state? I.e. for the purposes of
translation, pretend the FS state is DISABLED?
These bits are scarce, are we are nearly out.
r~
next prev parent reply other threads:[~2023-04-11 1:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-10 14:13 [RFC PATCH 0/4] Smstateen FCSR implementation Mayuresh Chitale
2023-04-10 14:13 ` [RFC PATCH 1/4] target/riscv: smstateen check for fcsr Mayuresh Chitale
2023-04-10 14:44 ` liweiwei
2023-04-14 5:41 ` Mayuresh Chitale
2023-04-10 14:13 ` [RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags Mayuresh Chitale
2023-04-11 1:47 ` Richard Henderson [this message]
2023-04-14 5:46 ` Mayuresh Chitale
2023-04-10 14:13 ` [RFC PATCH 3/4] target/riscv: check smstateen fcsr flag Mayuresh Chitale
2023-04-10 14:30 ` liweiwei
2023-04-14 5:42 ` Mayuresh Chitale
2023-04-11 1:52 ` Richard Henderson
2023-04-14 5:44 ` Mayuresh Chitale
2023-04-10 14:13 ` [RFC PATCH 4/4] target/riscv: smstateen knobs Mayuresh Chitale
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