From: "Cédric Le Goater" <clg@redhat.com>
To: Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org,
Dave Jiang <dave.jiang@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Alex Williamson <alex.williamson@redhat.com>,
Zhi Wang <zhiw@nvidia.com>
Subject: Re: [PATCH RFC 0/5] hw/cxl: Type 2 Device RFC
Date: Thu, 17 Oct 2024 18:57:00 +0200 [thread overview]
Message-ID: <5827f6e5-6de9-4ec1-83eb-b2e552092498@redhat.com> (raw)
In-Reply-To: <20230517-rfc-type2-dev-v1-0-6eb2e470981b@intel.com>
Hello,
On 5/18/23 04:45, Ira Weiny wrote:
> Type 2 devices are not yet a reality. Developing core kernel support
> is difficult without some test device to model against.
>
> Define a type 2 device 'cxl-accel'. This device is derived from the
> type 3 device and retains all that functionality for now.
>
> Mock up a couple of accelerator features (Back Invalidate [BI] and
> Unordered IO [UIO]) as examples for the RFC. These have no
> functionality other than to report the features as present for software
> to key off of.
>
> Defining these devices in qemu can be done with the following example:
>
> ...
> -device cxl-accel,bus=sw0p0,volatile-memdev=cxl-ac-mem5,id=cxl-dev5,sn=0xCAFE0005
> ...
>
> NOTE: I'm leaving off Michael Tsirkin for now because this is really
> rough and I'm mainly sending it out because it was talked about in the
> CXL community call on 5/16.
>
> Not-Yet-Signed-off-by: Ira Weiny <ira.weiny@intel.com>
A recent proposal to add support in VFIO for CXL passthrough uses
this emulated device and a sample driver for a proof of concept.
For this effort, it would be very useful to have a QEMU model for
a CXL type2 device, even partially implemented.
I haven't found any updates of this series. What are the plans for
upstream today ?
For vfio-cxl, see :
* [RFC] vfio: introduce vfio-cxl to support CXL type-2 accelerator passthrough
https://lore.kernel.org/kvm/20240920223446.1908673-1-zhiw@nvidia.com
* [RFC] Introduce vfio-cxl to support CXL type-2 device passthrough
https://lore.kernel.org/all/20240921071440.1915876-1-zhiw@nvidia.com/
Thanks,
C.
> ---
> Ira Weiny (5):
> hw/cxl: Use define for build bug detection
> hw/cxl: Refactor component register initialization
> hw/cxl: Derive a CXL accelerator device from Type-3
> hw/cxl/accel: Add Back-Invalidate decoder capbility structure
> hw/cxl: Add UIO HDM decoder register fields
>
> docs/system/devices/cxl.rst | 11 ++++++
> hw/cxl/cxl-component-utils.c | 80 +++++++++++++++++++-----------------------
> hw/mem/cxl_type3.c | 39 ++++++++++++++++++++
> include/hw/cxl/cxl_component.h | 51 +++++++++++++++++++--------
> include/hw/cxl/cxl_device.h | 16 +++++++++
> include/hw/pci/pci_ids.h | 1 +
> 6 files changed, 141 insertions(+), 57 deletions(-)
> ---
> base-commit: 8eb2a03258313f404ca0c8609a8f9009b9b4318c
> change-id: 20230517-rfc-type2-dev-c2d661a29d96
>
> Best regards,
next prev parent reply other threads:[~2024-10-17 16:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 2:45 [PATCH RFC 0/5] hw/cxl: Type 2 Device RFC Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 1/5] hw/cxl: Use define for build bug detection Ira Weiny
2023-05-18 9:54 ` Jonathan Cameron via
2023-05-18 20:19 ` Ira Weiny
2023-05-19 15:14 ` Jonathan Cameron via
2023-05-23 14:18 ` Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 2/5] hw/cxl: Refactor component register initialization Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 3/5] hw/cxl: Derive a CXL accelerator device from Type-3 Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 4/5] hw/cxl/accel: Add Back-Invalidate decoder capbility structure Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 5/5] hw/cxl: Add UIO HDM decoder register fields Ira Weiny
2024-10-17 16:57 ` Cédric Le Goater [this message]
2024-10-18 14:49 ` [PATCH RFC 0/5] hw/cxl: Type 2 Device RFC Zhi Wang
2024-10-18 15:25 ` Alejandro Lucero Palau
2024-10-18 16:19 ` Jonathan Cameron via
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