From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7432C02196 for ; Thu, 6 Feb 2025 07:23:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfwDm-0001SK-PL; Thu, 06 Feb 2025 02:22:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfwDk-0001Rf-MR; Thu, 06 Feb 2025 02:22:44 -0500 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfwDi-0007YQ-Lj; Thu, 06 Feb 2025 02:22:44 -0500 Received: from mail.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4YpT8660Srz4wyr; Thu, 6 Feb 2025 18:22:30 +1100 (AEDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (Client did not present a certificate) by mail.ozlabs.org (Postfix) with ESMTPSA id 4YpT826fXrz4wnp; Thu, 6 Feb 2025 18:22:26 +1100 (AEDT) Message-ID: <5856008e-a664-4f5c-a0c0-6813aaf8775a@kaod.org> Date: Thu, 6 Feb 2025 08:22:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 To: Jamin Lin , Andrew Jeffery , Peter Maydell , Steven Lee , Troy Lee , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: Troy Lee , Yunlin Tang References: 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List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > The design of the OR gates for GICINT 196 is as follows: > It has interrupt sources ranging from 0 to 31, with its output pin connected to > INTC_IO "T0 GICINT_196". > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and > its bit 4 output should be connected to GIC 196. > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following: > Bit 0 -> GIC 192 > Bit 1 -> GIC 193 > Bit 2 -> GIC 194 > Bit 3 -> GIC 195 > Bit 4 -> GIC 196 > > Jamin > |-------------------------------------------------------------------------------------------------------| > | AST2700 A1 Design | > | To GICINT196 | > | | > | ETH1 |-----------| |--------------------------| |--------------| | > | -------->|0 | | INTC_IO | | orgates[0] | | > | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | > | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | > | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | > | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | > | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | > | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | > | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | > | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | > | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | > | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | > | UART3 | 26| |--------------------------| |--------------| | | > | ---------|10 27| | | > | UART5 | 28| | | > | -------->|11 29| | | > | UART6 | | | | > | -------->|12 30| |-----------------------------------------------------------------------| | > | UART7 | 31| | | > | -------->|13 | | | > | UART8 | OR[0:31] | | |------------------------------| |----------| | > | -------->|14 | | | INTC | | GIC | | > | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | | > | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | | > | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | | > | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | | > | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | | > | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | | > | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | | > | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | | > | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | | > | |inpin[0:9]--------->outpin[9] |---------->|201 | | > |-------------------------------------------------------------------------------------------------------| > |-------------------------------------------------------------------------------------------------------| > | ETH1 |-----------| orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | | > | -------->|0 | orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | | > | ETH2 | 4| orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | | > | -------->|1 5| orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | | > | ETH3 | 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132 | | > | -------->|2 19| orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | | > | UART0 | 20| orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | | > | -------->|7 21| orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | | > | UART1 | 22| orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | | > | -------->|8 23| |------------------------------| |----------| | > | UART2 | 24| | > | -------->|9 25| AST2700 A0 Design | > | UART3 | 26| | > | -------->|10 27| | > | UART5 | 28| | > | -------->|11 29| GICINT132 | > | UART6 | | | > | -------->|12 30| | > | UART7 | 31| | > | -------->|13 | | > | UART8 | OR[0:31] | | > | -------->|14 | | > | UART9 | | | > | -------->|15 | | > | UART10 | | | > | -------->|16 | | > | UART11 | | | > | -------->|17 | | > | UART12 | | | > | -------->|18 | | > | |-----------| | > | | > |-------------------------------------------------------------------------------------------------------| Nice ! When you send the intc series for ast2700a1 support, could you please include this diagram in file docs/specs/aspeed-intc.rst with some description ? The text could be the same as the cover letter. Thanks, C.