From: Richard Henderson <richard.henderson@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com
Subject: Re: [PATCH v4 1/9] target/riscv: add rva22u64 profile definition
Date: Wed, 25 Oct 2023 16:48:00 -0700 [thread overview]
Message-ID: <585e307c-5c08-4bee-a9d3-2965c4be494f@linaro.org> (raw)
In-Reply-To: <20231025135001.531224-2-dbarboza@ventanamicro.com>
On 10/25/23 06:49, Daniel Henrique Barboza wrote:
> +/* Optional extensions left out: RVV, zfh, zkn, zks */
> +static RISCVCPUProfile RVA22U64 = {
const.
> + .name = "rva22u64",
> + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC,
> + .ext_offsets = {
> + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
> + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
> + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
> + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
> + CPU_CFG_OFFSET(ext_zicboz),
> +
> + RISCV_PROFILE_EXT_LIST_END
> + }
> +};
> +
> +RISCVCPUProfile *riscv_profiles[] = {
> + &RVA22U64, NULL,
> +};
const RISCVCPUProfile * const riscv_profiles[]
r~
next prev parent reply other threads:[~2023-10-25 23:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 13:49 [PATCH v4 0/9] RVA22U64 profile support Daniel Henrique Barboza
2023-10-25 13:49 ` [PATCH v4 1/9] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-25 16:05 ` Andrew Jones
2023-10-25 23:48 ` Richard Henderson [this message]
2023-10-25 23:49 ` Richard Henderson
2023-10-25 13:49 ` [PATCH v4 2/9] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-25 16:09 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 3/9] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-25 16:10 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 4/9] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-25 16:14 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 5/9] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-25 16:14 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-25 16:16 ` Andrew Jones
2023-10-25 13:49 ` [PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-25 16:18 ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-25 16:24 ` Andrew Jones
2023-10-25 13:50 ` [PATCH v4 9/9] target/riscv/tcg: warn if profile exts are disabled Daniel Henrique Barboza
2023-10-25 16:28 ` Andrew Jones
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=585e307c-5c08-4bee-a9d3-2965c4be494f@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).