From: Thomas Huth <thuth@redhat.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jonathan Cameron" <Jonathan.Cameron@Huawei.com>,
"Markus Armbruster" <armbru@redhat.com>
Cc: qemu-devel@nongnu.org, "Michael Tsirkin" <mst@redhat.com>,
"Ben Widawsky" <bwidawsk@kernel.org>,
linux-cxl@vger.kernel.org, linuxarm@huawei.com,
"Ira Weiny" <ira.weiny@intel.com>,
"Gregory Price" <gourry.memverge@gmail.com>,
"Mike Maslenkin" <mike.maslenkin@gmail.com>,
"Dave Jiang" <dave.jiang@intel.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>
Subject: Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
Date: Thu, 23 Feb 2023 07:58:18 +0100 [thread overview]
Message-ID: <586d040f-d712-905e-fd68-bcde3713478b@redhat.com> (raw)
In-Reply-To: <b9bd5698-1f73-b912-0344-4b70c30dd02a@linaro.org>
On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> +Thomas (meson) & Marc-André (conditional QAPI)
+ Markus
> On 22/2/23 17:49, Jonathan Cameron wrote:
>>>>>> +# Type of uncorrectable CXL error to inject. These errors are
>>>>>> reported via
>>>>>> +# an AER uncorrectable internal error with additional information
>>>>>> logged at
>>>>>> +# the CXL device.
>>>>>> +#
>>>>>> +# @cache-data-parity: Data error such as data parity or data ECC
>>>>>> error CXL.cache
>>>>>> +# @cache-address-parity: Address parity or other errors associated
>>>>>> with the
>>>>>> +# address field on CXL.cache
>>>>>> +# @cache-be-parity: Byte enable parity or other byte enable errors on
>>>>>> CXL.cache
>>>>>> +# @cache-data-ecc: ECC error on CXL.cache
>>>>>> +# @mem-data-parity: Data error such as data parity or data ECC error
>>>>>> on CXL.mem
>>>>>> +# @mem-address-parity: Address parity or other errors associated with
>>>>>> the
>>>>>> +# address field on CXL.mem
>>>>>> +# @mem-be-parity: Byte enable parity or other byte enable errors on
>>>>>> CXL.mem.
>>>>>> +# @mem-data-ecc: Data ECC error on CXL.mem.
>>>>>> +# @reinit-threshold: REINIT threshold hit.
>>>>>> +# @rsvd-encoding: Received unrecognized encoding.
>>>>>> +# @poison-received: Received poison from the peer.
>>>>>> +# @receiver-overflow: Buffer overflows (first 3 bits of header log
>>>>>> indicate which)
>>>>>> +# @internal: Component specific error
>>>>>> +# @cxl-ide-tx: Integrity and data encryption tx error.
>>>>>> +# @cxl-ide-rx: Integrity and data encryption rx error.
>>>>>> +##
>>>>>> +
>>>>>> +{ 'enum': 'CxlUncorErrorType',
>>>>>
>>>>> Doesn't these need
>>>>>
>>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>>>>
>>>>> ?
>>>>
>>>> If I make this change I get a bunch of
>>>>
>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned
>>>> "CONFIG_CXL_MEM_DEVICE"
>>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>>>
>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>>>
>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>>>>
>>>> To be honest though I don't fully understand the QEMU build system so
>>>> the reason
>>>> for the error might be wrong.
>>>
>>> You need to restrict to system emulation (the 'have_system' check):
>>
>> This doesn't help - still have
>> attempt to used poisoned "CONFIG_CXL"
Not sure how the QAPI generator works, but target specific config switches
can only be used in target specific json files there, so that's
machine-target.json and misc-target.json currently, as far as I know. Not
sure how the QAPI generator distinguishes between common and target specific
code, though ... just by the "-target" suffix? Maybe Markus or Marc-André
can comment on that.
See also:
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg01885.html
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg02001.html
Thomas
next prev parent reply other threads:[~2023-02-23 6:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron via
2023-02-21 22:06 ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron via
2023-02-21 22:08 ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron via
2023-02-21 15:48 ` Dave Jiang
2023-02-21 22:15 ` Philippe Mathieu-Daudé
2023-02-22 14:53 ` Jonathan Cameron via
2023-02-22 15:32 ` Philippe Mathieu-Daudé
2023-02-22 16:49 ` Jonathan Cameron via
2023-02-22 18:16 ` Philippe Mathieu-Daudé
2023-02-23 6:58 ` Thomas Huth [this message]
2023-02-23 7:37 ` Markus Armbruster
2023-02-23 14:27 ` Jonathan Cameron via
2023-02-24 17:37 ` Jonathan Cameron via
2023-02-24 19:02 ` Philippe Mathieu-Daudé
2023-02-27 9:40 ` Markus Armbruster
2023-02-22 18:28 ` Markus Armbruster
2023-10-27 4:54 ` Markus Armbruster
2023-10-31 17:55 ` Jonathan Cameron via
2023-10-31 17:55 ` Jonathan Cameron
2023-11-02 6:47 ` Markus Armbruster
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