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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 30/57] tcg/sparc64: Allocate %g2 as a third temporary Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org References: <20230503070656.1746170-1-richard.henderson@linaro.org> <20230503070656.1746170-31-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.802, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/5/23 13:19, Peter Maydell wrote: > On Wed, 3 May 2023 at 08:17, Richard Henderson > wrote: >> >> Signed-off-by: Richard Henderson >> --- >> tcg/sparc64/tcg-target.c.inc | 15 +++++++-------- >> 1 file changed, 7 insertions(+), 8 deletions(-) >> >> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc >> index e997db2645..64464ab363 100644 >> --- a/tcg/sparc64/tcg-target.c.inc >> +++ b/tcg/sparc64/tcg-target.c.inc >> @@ -83,9 +83,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { >> #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) >> #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) >> >> -/* Define some temporary registers. T2 is used for constant generation. */ >> +/* Define some temporary registers. T3 is used for constant generation. */ >> #define TCG_REG_T1 TCG_REG_G1 >> -#define TCG_REG_T2 TCG_REG_O7 >> +#define TCG_REG_T2 TCG_REG_G2 >> +#define TCG_REG_T3 TCG_REG_O7 >> >> #ifndef CONFIG_SOFTMMU >> # define TCG_GUEST_BASE_REG TCG_REG_I5 >> @@ -110,7 +111,6 @@ static const int tcg_target_reg_alloc_order[] = { >> TCG_REG_I4, >> TCG_REG_I5, >> >> - TCG_REG_G2, >> TCG_REG_G3, >> TCG_REG_G4, >> TCG_REG_G5, >> @@ -492,8 +492,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, >> static void tcg_out_movi(TCGContext *s, TCGType type, >> TCGReg ret, tcg_target_long arg) >> { >> - tcg_debug_assert(ret != TCG_REG_T2); >> - tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); >> + tcg_debug_assert(ret != TCG_REG_T3); >> + tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); >> } > > Why do we need to change this usage of TCG_REG_T2 but not > any of the others ? To match the comment above. r~