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(p200300faaf0bb200c875a4c76b3be6c4.dip0.t-ipconnect.de. [2003:fa:af0b:b200:c875:a4c7:6b3b:e6c4]) by smtp.gmail.com with ESMTPSA id 23-20020a170906329700b007821f4bc328sm644886ejw.178.2022.10.29.06.04.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 29 Oct 2022 06:04:05 -0700 (PDT) Date: Sat, 29 Oct 2022 13:04:00 +0000 From: Bernhard Beschow To: =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= , qemu-devel@nongnu.org CC: qemu-ppc@nongnu.org, Aurelien Jarno , Yoshinori Sato , Antony Pavlov , BALATON Zoltan , Alistair Francis , Bin Meng , Kevin Wolf , Peter Maydell , Jan Kiszka , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= , Hanna Reitz , qemu-arm@nongnu.org, Magnus Damm , "Edgar E. Iglesias" , qemu-block@nongnu.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v4_6/7=5D_hw/sd/sdhci=3A_Imp?= =?US-ASCII?Q?lement_Freescale_eSDHC_device_model?= In-Reply-To: <724F8CC8-C5E8-4785-B5C2-F1D327863717@gmail.com> References: <20221018210146.193159-1-shentey@gmail.com> <20221018210146.193159-7-shentey@gmail.com> <724F8CC8-C5E8-4785-B5C2-F1D327863717@gmail.com> Message-ID: <590683A5-2774-432C-A47A-ED755054479C@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 29=2E Oktober 2022 11:33:51 UTC schrieb Bernhard Beschow : >Am 27=2E Oktober 2022 21:40:01 UTC schrieb "Philippe Mathieu-Daud=C3=A9" = : >>Hi Bernhard, >> >>On 18/10/22 23:01, Bernhard Beschow wrote: >>> Will allow e500 boards to access SD cards using just their own devices= =2E >>>=20 >>> Signed-off-by: Bernhard Beschow >>> --- >>> hw/sd/sdhci=2Ec | 120 ++++++++++++++++++++++++++++++++++++++= +++- >>> include/hw/sd/sdhci=2Eh | 3 ++ >>> 2 files changed, 122 insertions(+), 1 deletion(-) >>>=20 >>> diff --git a/hw/sd/sdhci=2Ec b/hw/sd/sdhci=2Ec >>> index 306070c872=2E=2E8d8ad9ff24 100644 >>> --- a/hw/sd/sdhci=2Ec >>> +++ b/hw/sd/sdhci=2Ec >>> @@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s) >>> s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_dat= a_transfer, s); >>> s->io_ops =3D &sdhci_mmio_ops; >>> + s->io_registers_map_size =3D SDHC_REGISTERS_MAP_SIZE; >>> } >>> void sdhci_uninitfn(SDHCIState *s) >>> @@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error *= *errp) >>> s->fifo_buffer =3D g_malloc0(s->buf_maxsz); >>> memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdh= ci", >>> - SDHC_REGISTERS_MAP_SIZE); >>> + s->io_registers_map_size); >> >>I don't think we want to change this region size=2E [see below] >> >>> void sdhci_common_unrealize(SDHCIState *s) >>> @@ -1575,6 +1576,122 @@ static const TypeInfo sdhci_bus_info =3D { >>> =2Eclass_init =3D sdhci_bus_class_init, >>> }; >>> +/* --- qdev Freescale eSDHC --- */ >>> + >>> +/* Watermark Level Register */ >>> +#define ESDHC_WML 0x44 >>> + >>> +/* Control Register for DMA transfer */ >>> +#define ESDHC_DMA_SYSCTL 0x40c >>> + >>> +#define ESDHC_REGISTERS_MAP_SIZE 0x410 >> >>My preferred approach would be to create a container region with a >>size of ESDHC_REGISTERS_MAP_SIZE=2E Map the SDHC_REGISTERS_MAP region >>in the container at offset 0, priority -1=2E Add 2 register regions >>for ESDHC_WML and ESDHC_DMA_SYSCTL, and map them with priority 1 in >>the container=2E =2E=2E=2E >> >>> +static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned siz= e) >>> +{ >>> + uint64_t ret; >>> + >>> + switch (offset) { >>> + case SDHC_SYSAD: >>> + case SDHC_BLKSIZE: >>> + case SDHC_ARGUMENT: >>> + case SDHC_TRNMOD: >>> + case SDHC_RSPREG0: >>> + case SDHC_RSPREG1: >>> + case SDHC_RSPREG2: >>> + case SDHC_RSPREG3: >>> + case SDHC_BDATA: >>> + case SDHC_PRNSTS: >>> + case SDHC_HOSTCTL: >>> + case SDHC_CLKCON: >>> + case SDHC_NORINTSTS: >>> + case SDHC_NORINTSTSEN: >>> + case SDHC_NORINTSIGEN: >>> + case SDHC_ACMD12ERRSTS: >>> + case SDHC_CAPAB: >>> + case SDHC_SLOT_INT_STATUS: >>> + ret =3D sdhci_read(opaque, offset, size); >>> + break; >> >>=2E=2E=2E Then you don't need these cases=2E >> >>> + case ESDHC_WML: >>> + case ESDHC_DMA_SYSCTL: >>> + ret =3D 0; >>> + qemu_log_mask(LOG_UNIMP, "ESDHC rd @0x%02" HWADDR_PRIx >>> + " not implemented\n", offset); >> >>But then I realize you only treat these 2 registers as UNIMP=2E >> >>So now, I'd create 1 UNIMP region for ESDHC_WML and map it >>into SDHC_REGISTERS_MAP (s->iomem) with priority 1, and add >>another UNIMP region of ESDHC_REGISTERS_MAP_SIZE - SDHC_REGISTERS_MAP_SI= ZE (=3D 0x310) and map it normally at offset >>0x100 (SDHC_REGISTERS_MAP_SIZE)=2E Look at create_unimp() in >>hw/arm/bcm2835_peripherals=2Ec=2E >> >>But the ESDHC_WML register has address 0x44 and fits inside the >>SDHC_REGISTERS_MAP region, so likely belong there=2E 0x44 is the >>upper part of the SDHC_CAPAB register=2E These bits are undefined >>on the spec v2, which I see you are setting in esdhci_init()=2E >>So this register should already return 0, otherwise we have >>a bug=2E Thus we don't need to handle this ESDHC_WML particularly=2E My idea here was to catch this unimplemented case in order to indicate thi= s clearly to users=2E Perhaps it nudges somebody to provide a patch? >> >>And your model is reduced to handling create_unimp() in esdhci_realize()= =2E >> >>Am I missing something? > >The mmio ops are big endian and need to be aligned to a 4-byte boundary= =2E It took me quite a while to debug this=2E So shall I just create an add= itional memory region for the region above SDHC_REGISTERS_MAP_SIZE for ESDH= C_DMA_SYSCTL? All in all I currently don't have a better idea than keeping the custom i/= o ops for the standard region and adding an additional unimplemented region= for ESDHC_DMA_SYSCTL=2E I think I'd have to dynamically allocate memory fo= r it where I still need to figure out how not to leak it=2E Best regards, Bernhard > >Best regards, >Bernhard >> >>Regards, >> >>Phil=2E >