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Mon, 05 Jun 2023 03:16:37 -0700 (PDT) Message-ID: <596a040e-8d92-571f-5c18-618c707b6340@linaro.org> Date: Mon, 5 Jun 2023 12:16:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 15/15] hw/timer/arm_timer: QOM'ify ARM_TIMER Content-Language: en-US To: Mark Cave-Ayland , qemu-devel@nongnu.org, Peter Maydell Cc: Thomas Huth , qemu-arm@nongnu.org, Sergey Kambalin , =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20230531203559.29140-1-philmd@linaro.org> <20230531203559.29140-16-philmd@linaro.org> <43f014f5-6dd7-7c46-eea4-ed9cffe8ec48@ilande.co.uk> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/6/23 20:12, Mark Cave-Ayland wrote: > On 03/06/2023 19:07, Mark Cave-Ayland wrote: > >> On 31/05/2023 21:35, Philippe Mathieu-Daudé wrote: >> >>> Introduce the ARM_TIMER sysbus device. >>> >>> arm_timer_new() is converted as QOM instance init()/finalize() >>> handlers. Note in arm_timer_finalize() we release a ptimer handle >>> which was previously leaked. >>> >>> ArmTimerState is directly embedded into SP804State/IcpPitState, >>> and is initialized as a QOM child. >>> >>> Since the timer frequency belongs to ARM_TIMER, have it hold the >>> QOM property. SP804State/IcpPitState directly access it. >>> >>> Similarly the SP804State/IcpPitState input IRQ becomes the >>> ARM_TIMER sysbus output IRQ. >>> >>> Signed-off-by: Philippe Mathieu-Daudé >>> --- >>>   hw/timer/arm_timer.c | 109 +++++++++++++++++++++++++++---------------- >>>   1 file changed, 70 insertions(+), 39 deletions(-) >>> >>> diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c >>> index 82123b40c0..a929fbba62 100644 >>> --- a/hw/timer/arm_timer.c >>> +++ b/hw/timer/arm_timer.c >>> @@ -17,6 +17,7 @@ >>>   #include "qemu/module.h" >>>   #include "qemu/log.h" >>>   #include "qom/object.h" >>> +#include "qapi/error.h" >>>   /* Common timer implementation.  */ >>> @@ -29,14 +30,18 @@ >>>   #define TIMER_CTRL_PERIODIC     (1 << 6) >>>   #define TIMER_CTRL_ENABLE       (1 << 7) >>> -typedef struct { >>> +#define TYPE_ARM_TIMER "arm-timer" >>> +OBJECT_DECLARE_SIMPLE_TYPE(ArmTimerState, ARM_TIMER) >> >> As per our QOM guidelines ArmTimerState and the OBJECT_* macro should >> live in a separate header file. > > Ah wait: does "ArmTimerState is directly embedded into > SP804State/IcpPitState, and is initialized as a QOM child." mean that > ARM_TIMER is never instantiated externally? Correct, while the type is exposed as any QOM type, it is internal to the two devices, thus local to this unit. I don't mind exposing the state to have a consistent QOM style. What was discussed with Alex is: - We don't need to convert all non-QOM devices, but - Heterogeneous machines must contain only QOM devices; - If a non-QOM device forces incorrect API use or abuses, better convert it. >>> +struct ArmTimerState { >>> +    SysBusDevice parent_obj; >> >> And don't forget to add a blank line here too. OK. >>>       ptimer_state *timer; >>>       uint32_t control; >>>       uint32_t limit; >>>       uint32_t freq; >>>       int int_level; >>>       qemu_irq irq; >>> -} ArmTimerState; >>> +};